參數(shù)資料
型號(hào): PCA24S08DP
廠商: NXP SEMICONDUCTORS
元件分類: PROM
英文描述: 1024 ?8-bit CMOS EEPROM with access protection
中文描述: 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝: 3 MM, PLASTIC, SOT505-1, TSSOP-8
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 122K
代理商: PCA24S08DP
Philips Semiconductors
Product data
PCA24S08
1024
×
8-bit CMOS EEPROM with access protection
2004 May 10
4
DEVICE ADDRESSING
Following a START condition, the bus master must output the
address of the slave it is accessing. The address of the PCA24S08
is shown in Figure 3.
1
0
1
0
1
B2
B1
FIXED
SOFTWARE
SELECTABLE
R/W
SW02221
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read operation is selected, while
logic 0 selects a write operation. Bits B2 and B1 in the slave address
represent the 2 most significant bits of the word to be addressed.
The third device address bit in the I
2
C protocol that is usually
matched to A
2
(pin 3) on a standard 24C08 serial EEPROM is
internally connected HIGH, so device addresses A8h through AFh
(hex) are used to access the memory on the chip.
WRITE OPERATIONS
Write operations on the device can be performed only when WP is
held LOW. When WP pin is held HIGH, content of the full memory is
protected (Block 0 to Block 7, APP Registers, ID Page), and no write
operation is allowed.
Byte/word write:
Write command may be used to set the address
for a subsequent Read command. For a write operation, the
PCA24S08 requires a second address field. The address field
associated with the two software selectable bits in the slave address
is a word address providing access to the 1024 bytes of memory, as
shown in Figure 4. Upon receipt of the word address, the
PCA24S08 responds with an acknowledge and awaits the next
eight bits of data, again responding with an acknowledge. Word
address is automatically incremented. Figure 5 shows how the
memory array is addressed when the slave address byte and
address field byte are sent. The master terminates the transfer by
generating a STOP condition. After this STOP condition, the
Erase/Write (E/W) cycle starts and the I
2
C-bus is free for another
transmission. Up to 16 bytes of data can be written in the slave
writing sequence (E/W cycle).
1
0
1
0
1
B2
B1
FIXED
R/W
B0 P2
P1
P0
A3
A2
A1
A0
BLOCK 7
BLOCK 0
PAGE 0
PAGE 7
PAGE 0
PAGE 7
BYTE 0
BYTE 15
BYTE 0
BYTE 15
BYTE 0
BYTE 15
BYTE 0
BYTE 15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PAGE
NUMBER
BYTE
ADDRESS
BLOCK NUMBER
SW02222
Figure 4. Memory addressing
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