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參數(shù)資料
| 型號： | PCA24S08DP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PROM |
| 英文描述： | 1024 ?8-bit CMOS EEPROM with access protection |
| 中文描述： | 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | 3 MM, PLASTIC, SOT505-1, TSSOP-8 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 122K |
| 代理商： | PCA24S08DP |
Philips Semiconductors
Product data
PCA24S08
1024
×
8-bit CMOS EEPROM with access protection
2004 May 10
7
ACCESS PROTECTION
Write operation on the Access protection registers can be performed
when WP pin LOW. If the WP pin is HIGH all write operations are
prohibited from the serial port, although write commands may be
used to set the address for a subsequent read command.
All access protection bits are stored on a separate page of the
EEPROM that is not accesses using the normal commands of a
PCA24C08 memory. See the “Access Protection Page” section for
more detail on this information.
RFID ACCESS FIELDS (RF)
Even though the PCA24S08 does not have the RFID capability,
RFID access fields (RF) can be stored in order to keep existing
software compatibility. The fields are stored in the EEPROM and
organized as follows:
MSB
LSB
FUNCTION
0
0
No accesses permitted from RFID port
0
1
No accesses permitted from RFID port
1
0
Read only from RFID port
1
1
No restrictions for RFID accesses
PROTECTION BITS (PB)
The protection bits fields in the Access Protection Page determine
what type of accesses will be permitted via the serial port for each of
the blocks on the chip. If an illegal access is attempted, the
command will be NACK’ed. The MSB, if clear, prohibits all access to
the block, and the LSB if clear prohibits writes. The fields are stored
in the EEPROM and are organized as follows:
MSB
LSB
FUNCTION
0
0
No accesses permitted in the block
0
1
No accesses permitted in the block
1
0
Read only, writes cause a NACK
1
1
Read/write —No access constraints for
data within this block
Accessed within the Access Protection Page is an individual CMOS
Sticky Bit (SB) for each of the 8 blocks on the device. When the
value of the sticky bit is ‘0’, the Protection Bits (PB) for the
corresponding block may not be changed via the software. These
bits are all set to one when power is initially applied or when the
PROT pin is LOW. These sticky bits may be written only to a ‘0’ via
the serial interface using the standard serial write operations.
Reading the sticky bits does not affect their state.
Because permissions are set individually for each of the blocks, all
reads via serial port will only read bytes within the block that was
specified when the current address was latched in the device (with a
write command). The block address bits (B
2
or B
1
) that are sent with
the write command are ignored on a read command.
When a sticky bit is cleared (programmed at 0), the byte containing
the sticky bit cannot be changed anymore. If a write operation to this
byte is attempted, it will be normally acknowledged but no change
will happen in the byte value. The device does not go to an E/W
cycle and can be accessed immediately.
If a block is protected and only read operation is allowed (the
corresponding APP register has its PB bits programmed to 10), a
write operation to this block is not acknowledged (Slave Address
and Register pointer only are acknowledged). The device does not
go to an E/W cycle and can be accessed immediately.
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
This applies to:
–
EEPROM Block 0 to Block 7, controlled by PB
0
to PB
7
–
The last 7 bytes of the APP block (09H to 0FH) and the
ID page (10H to 1FH) controlled by PBAP
If a block is protected and neither read operation nor write operation
is allowed (the corresponding APP register has its PB bits
programmed to 00 or 01), a write operation to this block is not
acknowledged (Slave Address and Register pointer only are
acknowledged).
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
A read operation to this block is not allowed.
S – Addr+W – ACK – Reg Pointer – ACK – Sr – Addr+R – NACK
S – Addr+W – ACK – Reg Pointer – ACK – P – S – Addr+R – NACK
This applies to:
–
EEPROM Block 0 to Block 7, controlled by PB
0
to PB
7
–
The last 7 bytes of the APP block (09H to 0FH) and the
ID page (10H to 1FH) controlled by PBAP
BLOCK 0 WRITE PROTECTION BITS
The PCA24S08 provides a mechanism to divide block 0 into eight
128-bit (16 byte) pages that can be individually protected against
writes. These eight write protection (WPN) bits are stored within a
byte of the access protection page and are organized such that the
LSB protects the first 128 bits and so on. If a bit in this byte is set to
a one and the PB
0
field is set to 11, then writes are permitted on the
page corresponding to the WPN bit. If the WPN bit is set to a 0 or
the PB
0
is any value other than 11, then writes are not permitted in
that page.
The Write Protection hierarchy for serial accesses is shown in
Figure 6. In this drawing the bits within the boxes to the left of the
arrows are the only thing that determine whether or not the bit in the
box to the right of the arrow can be written. Read access control is
not shown in this diagram. Addresses listed in this diagram are for
the serial port assuming that the R/W bit in the command byte is set
to ‘0’.
For example, when SB
1
is a 1, the PB
1
field can be written to any
value by the system. When the PB
1
field is 11, Block 1 can be
written to by the system. Note that the state of the SB
1
bit does not
affect whether or not Block 1 can be written.
There is no individual page Write Protection for any other block
other than block 0 within the device. Within the remaining blocks on
the chip, access permissions are controlled on a block basis (BP
bits) or full chip basis (WP pin) only.
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| PCA24S08DP-T | 功能描述:電可擦除可編程只讀存儲器 1024X8 CMOS 電可擦除可編程只讀存儲器 ACCESS PROT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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