參數(shù)資料
型號(hào)： PCA24S08DP
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： PROM
英文描述： 1024 ?8-bit CMOS EEPROM with access protection
中文描述： 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝： 3 MM, PLASTIC, SOT505-1, TSSOP-8
文件頁(yè)數(shù)： 5/16頁(yè)
文件大小： 122K
代理商： PCA24S08DP
Philips Semiconductors
Product data
PCA24S08
1024
×
8-bit CMOS EEPROM with access protection
2004 May 10
5
The general command encoding used by the serial port for
EEPROM accesses is shown below in Device Access Examples,
where B
2-0
is the block number, P
2-0
is the page number within the
block and A
3-0
is the byte address within the page. Bits denoted as
“x” are ignored by the device.
1
B2
1
0
B1
1
0
S
0
A
A
ACKNOWLEDGE
FROM SLAVE
R/W
DATA
A0
B0 P2
P1
P0
A3
A2 A1
P
A
DATA
A
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
WORD
ADDRESS
WORD
ADDRESS
AUTO INCREMENT
WORD ADDRESS
AUTO INCREMENT
WORD ADDRESS
SW02103
Figure 5. Auto-increment memory word address; two byte write
Page write:
The PCA24S08 is capable of a 16-byte page write
operation. It is initiated in the same manner as the byte write
operation. The master can transit 16 data bytes within one
transmission. After receipt of each byte, the PCA24S08 will respond
with an acknowledge. The typical E/W time in this mode is 5 ms.
After the receipt of each data byte, the four low-order bits of the
word address are internally incremented. The six high-order bits of
the address remain unchanged. The slave acknowledges the
reception of each data byte with an ACK. The I
2
C-bus data transfer
is terminated by the master after the 16
th
byte of data with a STOP
condition. After a write to the last byte in a page, the internal
address is wrapped around to point to the beginning of that page. If
the master transmits more than 16 bytes prior to generating the
STOP condition, no acknowledge will be given on the 17
th
(and
following) data bytes and the whole transmission will be ignored and
no programming will be done. As in the byte write operation, all
inputs are disabled until completion of the internal write cycles.
After this STOP condition, the E/W cycle starts and the I
2
C-bus is
free for another transmission.
During the E/W cycle the slave receiver does not acknowledge if
addressed via the I
2
C-bus.
1
B2
1
0
B1
1
0
S
0
A
A
ACKNOWLEDGE
FROM SLAVE
R/W
DATA
A0
B0 P2
P1
P0
A3
A2 A1
P
A
DATA + 1
A
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
WORD
ADDRESS
WORD
ADDRESS
AUTO INCREMENT
WORD ADDRESS
AUTO INCREMENT
WORD ADDRESS
SW02104
A
DATA + 15
A
AUTO INCREMENT
WORD ADDRESS
LAST BYTE
ACKNOWLEDGE
FROM SLAVE
Figure 6. Page write operation: 16 bytes
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