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參數(shù)資料
型號(hào)： PCA9500PW,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 24/26頁(yè)
文件大小： 0K
描述： IC I/O EXPANDER I2C 8B 16TSSOP
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 96
接口： I²C，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 無(wú)
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.5 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
包括： EEPROM，POR
產(chǎn)品目錄頁(yè)面： 824 (CN2011-ZH PDF)
其它名稱： 568-1025-5
935271534112
PCA9500PW
PCA9500_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2009
7 of 26
NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
7.3.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current
source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into
heavily loaded outputs. These devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should be HIGH before being used as
inputs. See Figure 9.
7.4 Memory operations
7.4.1 Write operations
Write operations require an additional address eld to indicate the memory address
location to be written. The address eld is eight bits long, providing access to any one of
the 256 words of memory. There are two types of write operations, ‘byte write’ and
‘page write’.
Write operation is possible when the Write Control pin (WC) is put at a LOW logic level (0).
When this control signal is set at 1, write operation is not possible and data in the memory
is protected.
‘Byte write’ and ‘page write’ explained below assume that WC is set to 0.
7.4.1.1
Byte write
To perform a byte write the START condition is followed by the memory slave address and
the R/W bit set to 0. The PCA9500 will respond with an acknowledge and then consider
the next eight bits sent as the word address and the eight bits after the word address as
the data. The PCA9500 will issue an acknowledge after the receipt of both the word
address and the data. To terminate the data transfer the master issues the STOP
condition, initiating the internal write cycle to the non-volatile memory. Only write and read
operations to the quasi-bidirectional I/Os are allowed during the internal write cycle.
Fig 9.
Transient pull-up current (IOHt) while IO3 changes from LOW to HIGH and back to LOW
0
A
S
slave address (I/O expander)
START condition
R/W
acknowledge
from slave
002aae593
1
data to port
A
acknowledge
from slave
12345678
SCL
9
SDA
0
A
IO3 output voltage
IO3 pull-up output current
acknowledge
from slave
data to port
1
0
A2 A1 A0
0
IO3
P
STOP
condition
IO3
IOHt
IOH
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