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參數(shù)資料
型號: PCA9502BS,151
廠商: NXP Semiconductors
文件頁數(shù): 24/25頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C/SPI 24HVQFN
產(chǎn)品培訓模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 490
接口: I²C,SPI
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應商設備封裝: 24-HVQFN(4x4)
包裝: 托盤
產(chǎn)品目錄頁面: 824 (CN2011-ZH PDF)
其它名稱: 568-3635
935281363151
PCA9502BS-S
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
8 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
There is an exception to the ‘a(chǎn)cknowledge after every byte’ rule. It occurs when a master
is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
9.2 Addressing and transfer formats
Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
rst byte transmitted by the master after the START condition.
An address on the network is seven bits long, appearing as the most signicant bits of the
address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is
transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete
data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is
shown in Figure 8.
Fig 6.
Data transfer on the I2C-bus
S
P
SDA
SCL
MSB
0
1
6
7
8
0
1
2 to 7
8
ACK
002aab012
START
condition
STOP
condition
acknowledgement signal
from receiver
byte complete,
interrupt within receiver
clock line held LOW
while interrupt is serviced
Fig 7.
Acknowledge on the I2C-bus
S
01
6
7
8
002aab013
data output
by transmitter
data output
by receiver
SCL from master
START
condition
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
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