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參數(shù)資料
型號(hào): PCA9502BS,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 4/25頁(yè)
文件大小: 0K
描述: IC I/O EXPANDER I2C/SPI 24HVQFN
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 490
接口: I²C,SPI
輸入/輸出數(shù): 8
中斷輸出: 無(wú)
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-HVQFN(4x4)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 824 (CN2011-ZH PDF)
其它名稱: 568-3635
935281363151
PCA9502BS-S
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
12 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
The register read cycle (see Figure 11) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following sub-address.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal sub-address will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
White block: host to PCA9502
Grey block: PCA9502 to host
Fig 10. Master writes to slave
S
SLAVE ADDRESS
002aab047
W
A
REGISTER ADDRESS
A
nDATA
A
P
White block: host to PCA9502
Grey block: PCA9502 to host
Fig 11. Master read from Slave
S
SLAVE ADDRESS
002aab048
W
A
REGISTER ADDRESS
A
NA
P
S
SLAVE ADDRESS
R
A
nDATA
A
LAST DATA
Table 12.
Register address byte (I2C-bus)
Bit
Name
Function
7
-
not used
6:3
A[3:0]
internal register select
2:1
-
not used, set to 0
0
-
not used
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