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參數(shù)資料
型號: PCA9502BS,151
廠商: NXP Semiconductors
文件頁數(shù): 9/25頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C/SPI 24HVQFN
產(chǎn)品培訓模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 490
接口: I²C,SPI
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應商設備封裝: 24-HVQFN(4x4)
包裝: 托盤
產(chǎn)品目錄頁面: 824 (CN2011-ZH PDF)
其它名稱: 568-3635
935281363151
PCA9502BS-S
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
17 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
Table 17.
SPI-bus timing specications
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = 40 °Cto+85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.
All output load = 25 pF, unless otherwise specied.
Symbol
Parameter
Conditions
VDD = 2.5 V
VDD = 3.3 V
Unit
Min
Max
Min
Max
td(CS_NH-SOZ)
CS HIGH to SO 3-state delay time
CL = 100 pF
-
100
-
100
ns
tsu(CS_N-SCLK)
CS to SCLK setup time
100
-
100
-
ns
th(CS_N-SCLK)
CS to SCLK hold time
20
-
20
-
ns
td(SCLK-SO)
SCLK fall to SO valid delay time
CL = 100 pF
-
25
-
20
ns
tsu(SI-SCLK)
SI to SCLK setup time
10
-
20
-
ns
th(SI-SCLK)
SI to SCLK hold time
10
-
10
-
ns
TSCLK
SCLK period
tSCLKL + tSCLKL
83
-
67
-
ns
tSCLKH
SCLK HIGH time
30
-
25
-
ns
tSCLKL
SCLK LOW time
30
-
25
-
ns
tw(CS_NH)
CS HIGH pulse width
200
-
200
-
ns
td9
SPI output data valid time
200
-
200
-
ns
td13
SPI interrupt clear time
200
-
200
-
ns
Fig 16. Detailed SPI-bus timing
th(CS_N-SCLK) tsu(CS_N-SCLK)
tSCLKL
tSCLKH
th(CS_N-SCLK)
td(SCLK-SO)
td(CS_N-SOZ)
tsu(SI-SCLK)
th(SI-SCLK)
SO
SI
SCLK
CS
002aac429
tw(CS_NH)
R/W = 0; A[3:0] = IOState (0x0B)
Fig 17. SPI write IOState to GPIO switch
SI
A1
A2
A3
R/W
SCLK
0
A0
X
0
002aab878
GPIOn
D6
D7
D4
D5
D2
D3
D0
D1
CS
td9
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