參數(shù)資料
型號(hào)： PCA9505DGG,112
廠商： NXP Semiconductors
文件頁數(shù)： 3/34頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 40B 56TSSOP
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 35
接口： I²C
輸入/輸出數(shù)： 40
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 管件
包括： POR
產(chǎn)品目錄頁面： 824 (CN2011-ZH PDF)
其它名稱： 568-4244-5
935284486112
PCA9505DGG
PCA9505_9506
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2010
11 of 34
NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
7.3.2 OP0 to OP4 - Output Port registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
7.3.3 PI0 to PI4 - Polarity Inversion registers
These registers allow inversion of the polarity of the corresponding Input Port register.
Px[y] = 0: The corresponding Input Port register data polarity is retained.
Px[y] = 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 5.
OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
08h
OP0
7 to 0
O0[7:0]
R/W
0000 0000*
Output Port register bank 0
09h
OP1
7 to 0
O1[7:0]
R/W
0000 0000*
Output Port register bank 1
0Ah
OP2
7 to 0
O2[7:0]
R/W
0000 0000*
Output Port register bank 2
0Bh
OP3
7 to 0
O3[7:0]
R/W
0000 0000*
Output Port register bank 3
0Ch
OP4
7 to 0
O4[7:0]
R/W
0000 0000*
Output Port register bank 4
Table 6.
PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
10h
PI0
7 to 0
P0[7:0]
R/W
0000 0000*
Polarity Inversion register bank 0
11h
PI1
7 to 0
P1[7:0]
R/W
0000 0000*
Polarity Inversion register bank 1
12h
PI2
7 to 0
P2[7:0]
R/W
0000 0000*
Polarity Inversion register bank 2
13h
PI3
7 to 0
P3[7:0]
R/W
0000 0000*
Polarity Inversion register bank 3
14h
PI4
7 to 0
P4[7:0]
R/W
0000 0000*
Polarity Inversion register bank 4
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