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參數(shù)資料
型號(hào)： PCA9555BS,118
廠商： NXP Semiconductors
文件頁數(shù)： 6/34頁
文件大小： 0K
描述： IC I/O EXPANDER I2C 16B 24HVQFN
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 1
接口： I²C，SM 總線
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-HVQFN（4x4）
包裝： 標(biāo)準(zhǔn)包裝
包括： POR
產(chǎn)品目錄頁面： 826 (CN2011-ZH PDF)
配用： 568-4002-ND - DEMO BOARD I2C
其它名稱： 568-2382-6
PCA9555_8
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
14 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins changes state and
the pin is congured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read (see Figure 13). A pin congured as an
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
7.
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is dened as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is dened as the STOP
condition (P) (see Figure 16).
Fig 15. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 16. Denition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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PCA9555D/G-T 功能描述:IC I/O EXPANDER I2C 16B 24SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - I/O 擴(kuò)展器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 接口:I²C，JTAG 輸入/輸出數(shù):9 中斷輸出:無 頻率 - 時(shí)鐘:400kHz 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 包括:EEPROM
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