參數(shù)資料
型號(hào)： PCD5002
廠商： NXP Semiconductors N.V.
英文描述： Advanced POCSAG and APOC-1 Paging Decoder
中文描述： 高級(jí)POCSAG碼和載脂蛋白C - 1尋呼解碼器
文件頁(yè)數(shù)： 20/48頁(yè)
文件大?。?/td> 203K
代理商： PCD5002
1997 Jun 24
20
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 16
Index register
Notes
1.
2.
The index register only uses the least significant nibble, the upper 4 bits are ignored.
Writing to registers 0B to 0F has no effect, reading produces meaningless data.
ADDRESS
(1)
REGISTER FUNCTION
ACCESS
00H
00H
01H
02H
03H
04H
05H
05H
06H
07H
08H
09H
0AH
status
control
R
W
real time clock: seconds
real time clock:
1
100
second
alert cadence
alert set-up
periodic interrupt modulus
periodic interrupt counter
RAM write address pointer
EEPROM address pointer
RAM read address pointer
RAM data output
EEPROM data input/output
unused
R/W
R/W
W
W
W
R
R
R/W
R/W
R
R/W
note 2
0BH to 0FH
8.26
External interrupt
The PCD5002 can signal events to an external controller
via an interrupt signal at output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
Interrupts are generated by the following events (more
than one event is possible):
Call data available for output (bit D2)
SRAM pointers becoming equal (bit D3)
Expiry of periodic time-out (bit D7)
Expiry of alert time-out (bit D4)
Change of state in out-of-range indicator (bit D5)
Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
Immediate interrupts are generated by status bits D3,
D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6
(BAT monitoring) generate interrupts as soon as the
receiver is disabled (RXE = 0).
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position.
The interrupt output INT is reset after completion of a
status read operation.
8.27
Status/Control register
The status/control register consists of two independent
registers, one for reading (status) and one for writing
(control).
The status register shows the current operating condition
of the decoder and the cause(s) of an external interrupt.
The control register activates/deactivates certain
functions. Tables 17 and 18 show the bit allocations of
both registers.
All status bits will be reset after a status read operation
except for the out-of-range, battery-low and receiver
enable indicator bits (see note 1 to Table 17).
相關(guān)PDF資料
PDF描述
PCD5002H Advanced POCSAG and APOC-1 Paging Decoder
PCD5 Fuse
PCB1 Fuse
PCB2 Fuse
PCB2.5 Fuse
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCD5002A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for APOC1/POCSAG
PCD5002AH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for APOC1/POCSAG
PCD5002H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder
PCD5002HBD-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder
PCD5002HBD-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*