參數(shù)資料
型號： PCD5002
廠商： NXP Semiconductors N.V.
英文描述： Advanced POCSAG and APOC-1 Paging Decoder
中文描述： 高級POCSAG碼和載脂蛋白C - 1尋呼解碼器
文件頁數(shù)： 39/48頁
文件大?。?/td> 203K
代理商： PCD5002
1997 Jun 24
39
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Notes
1.
32768 Hz reference signal; 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods
(pulse duration: t
RFP
). The timing is shown in Fig.15.
50 Hz reference signal: square wave.
Duration depends on programmed bit rate; after reset t
ZSU
= 1.5 bits.
Nominal values; pause in 12th data bit (see Table 11).
2.
3.
4.
POCSAG data timing (1200 bits/s)
f
DI
t
BIT
t
CW
t
PA
t
BAT
data input rate
bit duration
codeword duration
preamble duration
batch duration
SPF byte 01H; D5 = 1; D4 = 0
480
1200
833.3
26.7
453.3
bits/s
μ
s
ms
ms
ms
POCSAG data timing (2400 bits/s)
f
DI
t
BIT
t
CW
t
PA
t
BAT
data input rate
bit duration
codeword duration
preamble duration
batch duration
SPF byte 01H; D5 = 1; D4 = 1
240
2400
416.6
13.3
226.6
bits/s
μ
s
ms
ms
ms
APOC-1 batch timing
t
SB
cycle duration
SPF byte 00H; bit D2 = 0
(5 batches)
SPF byte 00H; bit D2 = 0
(15 batches)
2720
bits
8160
bits
Synthesizer control
t
ZSU
f
ZSC
t
ZCL
t
ZSD
t
ZDS
t
ZDL1
t
ZLE
t
ZDL2
synthesizer set-up duration
output clock frequency
clock pulse duration
data bit duration
data bit set-up time
data load enable delay
load enable pulse duration
inter block delay
oscillator running; note 3
note 4
1
38400
13.02
26.04
13.02
91.15
13.02
117.19
2
bits
Hz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
note 4
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
相關(guān)PDF資料
PDF描述
PCD5002H Advanced POCSAG and APOC-1 Paging Decoder
PCD5 Fuse
PCB1 Fuse
PCB2 Fuse
PCB2.5 Fuse
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