參數(shù)資料
型號: PCF8562
廠商: NXP Semiconductors N.V.
英文描述: Universal LCD driver for low multiplex rates
中文描述: 通用LCD驅(qū)動器的低復(fù)用率
文件頁數(shù): 28/36頁
文件大?。?/td> 928K
代理商: PCF8562
November 22, 2004
28
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
11 AC CHARACTERISTICS
V
DD
= 1.8 to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 to 6.5 V; T
amb
=
40 to
+
85
°
C; unless otherwise specified.
Notes
1.
2.
3.
Typical output duty factor: 50% measured at the CLK output pin.
Not tested in production.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
CLK
t
CLKH
t
CLKL
t
PD(SYNC)
t
SYNCL
t
PD(LCD)
oscillator frequency
input CLK HIGH time
input CLK LOW time
SYNC propagation delay
SYNC LOW time
driver delays with test loads
note 1
960
60
60
1
1890
30
2640
30
Hz
μ
s
μ
s
ns
μ
s
μ
s
V
LCD
= 5 V; note 2
Timing characteristics: I
2
C-bus;
note 3
f
SCL
t
BUF
t
HD;STA
t
SU;STA
t
LOW
t
HIGH
t
r
t
f
C
B
t
SU;DAT
t
HD;DAT
t
SU;STO
t
SW
SCL clock frequency
bus free time between a STOP and START
START condition hold time
set-up time for a repeated START condition
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
data set-up time
data hold time
set-up time for STOP condition
tolerable spike width on bus
1.3
0.6
0.6
1.3
0.6
100
0
0.6
400
0.3
0.3
400
50
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
pF
ns
ns
μ
s
ns
Fig.18 Test loads.
handbook, full pagewidth
MCE439v2
3.3 k
1.5 k
0.5VDD
VDD
VSS
SDA,
SCL
CLK
1 nF
BP0to BP3, and
S0to S31
(2%)
(2%)
6.8
VDD
SYNC
(2%)
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