參數(shù)資料
型號(hào)： PCI1520I
廠商： Texas Instruments, Inc.
英文描述： PC CARD CONTROLLERS
中文描述： PC卡控制器
文件頁數(shù)： 112/138頁
文件大小： 745K
代理商： PCI1520I
516
5.14 ExCA Memory Windows 04 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 511 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA memory windows 04 start-address high-byte
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus socket address + 811h; Card A ExCA offset 11h
Card B ExCA offset 51h
Register:
Offset:
ExCA memory window 1 start-address high-byte
CardBus socket address + 819h; Card A ExCA offset 19h
Card B ExCA offset 59h
Register:
Offset:
ExCA memory window 2 start-address high-byte
CardBus socket address + 821h; Card A ExCA offset 21h
Card B ExCA offset 61h
Register:
Offset:
ExCA memory window 3 start-address high-byte
CardBus socket address + 829h; Card A ExCA offset 29h
Card B ExCA offset 69h
Register:
Offset:
ExCA memory window 4 start-address high-byte
CardBus socket address + 831h; Card A ExCA offset 31h
Card B ExCA offset 71h
Type:
Default:
Read/Write
00h
Table 511. ExCA Memory Windows 04 Start-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
7
DATASIZE
RW
Data size. Bit 7 controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
6
ZEROWAIT
RW
Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing
emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
16-bit cycles are reduced to equivalent of two ISA cycles.
54
SCRATCH
RW
Scratch pad bits. Bits 5 and 4 have no effect on memory window operation.
30
STAHN
RW
Start-address high nibble. Bits 30 represent the upper address bits A23A20 of the memory window
start address.
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