參數(shù)資料
型號： PCI1520I
廠商： Texas Instruments, Inc.
英文描述： PC CARD CONTROLLERS
中文描述： PC卡控制器
文件頁數(shù)： 74/138頁
文件大?。?/td> 745K
代理商： PCI1520I
412
4.22 I/O Limit Registers 0, 1
The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the PCI1520
to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to PCI.
The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are
a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 152 are read/write and allow
the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 3116 of the appropriate I/O base)
on doubleword boundaries.
Bits 3116 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1 and 0 are
read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write
transactions to read-only bits have no effect. The PCI1520 assumes that the lower 2 bits of the limit address are 1s.
NOTE:
The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
I/O limit registers 0, 1
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
I/O limit registers 0, 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
I/O limit registers 0, 1
30h, 38h
Read-only, Read/Write
0000 0000h
4.23 Interrupt Line Register
The interrupt line register communicates interrupt line routing information. Each PCI1520 function has an interrupt
line register.
Bit
7
6
5
4
3
2
1
0
Name
Interrupt line
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
Register:
Offset:
Type:
Default:
Interrupt line
3Ch
Read/Write
FFh
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