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| 型號(hào)： | PCI1520I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD CONTROLLERS |
| 中文描述： | PC卡控制器 |
| 文件頁(yè)數(shù)： | 76/138頁(yè) |
| 文件大?。?/td> | 745K |
| 代理商： | PCI1520I |
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414
4.25 Bridge Control Register
The bridge control register provides control over various PCI1520 bridging functions. Some bits in this register are
global and are accessed only through function 0. See Table 47 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Bridge control
Type
R
R
R
R
R
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
Default
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Bridge control
3Eh (functions 0, 1)
Read-only, Read/Write
0340h
Table 47. Bridge Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
1511
RSVD
R
Reserved. Bits 1511 return 0s when read.
10
POSTEN
RW
Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables
posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not. Bit 10 is socket
dependent and is not shared between functions 0 and 1.
9
PREFETCH1
RW
Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket
dependent. Bit 9 is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
8
PREFETCH0
RW
Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
7
INTR
RW
PCI interrupt IREQ routing enable. Bit 7 selects whether PC Card functional interrupts are routed to PCI
interrupts or the IRQ specified in the ExCA registers.
0 = Functional interrupts routed to PCI interrupts (default)
1 = Functional interrupts routed by ExCAs
6
CRST
RW
CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted
by passing a PRST assertion to CardBus.
0 = CRST deasserted
1 = CRST asserted (default)
5
MABTMODE
RW
Master abort mode. Bit 5 controls how the PCI1520 responds to a master abort when the PCI1520 is an
initiator on the CardBus interface. This bit is common between each socket.
0 = Master aborts not reported (default)
1 = Signal target abort on PCI and SERR (if enabled)
4
RSVD
R
Reserved. Bit 4 returns 0 when read.
3
VGAEN
RW
VGA enable. Bit 3 affects how the PCI1520 responds to VGA addresses. When this bit is set, accesses
to VGA addresses are forwarded.
2
ISAEN
RW
ISA mode enable. Bit 2 affects how the PCI1520 passes I/O cycles within the 64-Kbyte ISA range. This
bit is not common between sockets. When this bit is set, the PCI1520 does not forward the last 768 bytes
of each 1K I/O range to CardBus.
1
CSERREN
RW
CSERR enable. Bit 1 controls the response of the PCI1520 to CSERR signals on the CardBus bus. This
bit is common between the two sockets.
0 = CSERR is not forwarded to PCI SERR.
1 = CSERR is forwarded to PCI SERR.
0
CPERREN
RW
CardBus parity error response enable. Bit 0 controls the response of the PCI1520 to CardBus parity errors.
This bit is common between the two sockets.
0 = CardBus parity errors are ignored.
1 = CardBus parity errors are reported using CPERR.
This bit is global and is accessed only through function 0.
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