參數(shù)資料
型號: PCM1602APTG4
廠商: Texas Instruments
文件頁數(shù): 24/46頁
文件大?。?/td> 0K
描述: IC DAC 24BIT 6CH 192KHZ 48-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 250
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 模擬和數(shù)字
功率耗散(最大): 240mW
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 6 電壓,單極
采樣率(每秒): 192k
配用: DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
www.ti.com
ZERO FLAG
Zero-Detect Condition
Zero detection for each output channel is independent from the others. If the data for a given channel remains at
a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.
Zero Output Flags
Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are set
to a logic-1 state. Each channel, ZERO1 through ZERO6 (pins 1 through 6), has zero-flag pins. In addition, all six
zero flags are logically ANDed together, and the result is provided at the ZEROA pin (pin 48), which is set to a
logic-1 state when all channels indicate a zero-detect condition. The zero-flag pins can be used to operate
external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally
controlled function.
The active polarity of the zero-flag output can be inverted by setting to 1 the ZREV bit of control register 10. The
reset default is active-high output, or ZREV = 0.
30
Copyright 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): PCM1602A
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