tw(SCKH) System Clock tw(SCKL) 2 V 0.8 V H L System Cloc" />
參數(shù)資料
型號： PCM1602APTG4
廠商： Texas Instruments
文件頁數(shù)： 5/46頁
文件大小： 0K
描述： IC DAC 24BIT 6CH 192KHZ 48-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 6
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 240mW
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 6 電壓，單極
采樣率（每秒）： 192k
配用： DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602
tw(SCKH)
System Clock
tw(SCKL)
2 V
0.8 V
H
L
System Clock
Pulse Cycle
Time(1)
T0005A08
www.ti.com
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1602A requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI input (pin 38). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. The PLL170x multiclock generator from Texas Instruments is
an excellent choice for providing the PCM1602A system clock.
The 192-kHz sampling frequency operation is available on DATA1 for VOUT1 and VOUT2. It is recommended that
VOUT3, VOUT4, VOUT5, and VOUT6 be forced to the bipolar zero level using the DAC3, DAC4, DAC5, and DAC6
bits of register 8 when operating at 192 kHz.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
(kHz)
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
8
(1)
2.048
3.072
4.096
6.144
16
(1)
4.096
6.144
8.192
12.288
32
(1)
8.192
12.288
16.384
24.576
44.1
(1)
11.2896
16.9344
22.5792
33.8688
48
(1)
12.288
18.432
24.576
36.864
96
(1)
24.576
36.864
49.152
(1)
192
24.576
36.864
(1)
This system clock is not supported for the given sampling frequency.
SYMBOL
PARAMETER
MIN
MAX
UNIT
tw(SCKH)
System clock pulse duration, HIGH
7
ns
tw(SCKL)
System clock pulse duration, LOW
7
ns
(1)
1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, and 1/768 fS.
Figure 19. System Clock Timing
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at the SCKO output (pin 39). SCKO can operate at
either full (fSCKI) or half (fSCKI/2) rate. The SCKO output frequency can be programmed using the CLKD bit of
register 9. The SCKO output pin can also be enabled or disabled using the CLKE bit of register 9. If the SCKO
output is not required, it is recommended to disable it using the CLKE bit. The default is SCKO enabled.
Copyright 2005–2010, Texas Instruments Incorporated
13
Product Folder Link(s): PCM1602A
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