Z–1 + 8-Level Quantizer Z–1 IN
參數(shù)資料
型號： PCM1602APTRG4
廠商： Texas Instruments
文件頁數(shù)： 30/46頁
文件大?。?/td> 0K
描述： IC DAC 24BIT 6CH 192KHZ 48-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 6
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 240mW
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 6 電壓，單極
采樣率（每秒）： 192k
配用： DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602
B0008-03
+
Z–1
+
8-Level Quantizer
Z–1
IN
8 fS
OUT
64 fS
+
Z–1
+
Z–1
+
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
www.ti.com
THEORY OF OPERATION
The DAC section of the PCM1602A is based on a multi-bit delta-sigma architecture. This architecture uses a
fourth-order noise shaper and an 8-level amplitude quantizer, followed by an analog low-pass filter. A block
diagram of the delta-sigma modulator is shown in Figure 36. This architecture has the advantage of stability and
improved jitter tolerance, when compared to traditional 1-bit (2-level) delta-sigma designs.
Figure 36. Eight-Level Delta-Sigma Modulator
The combined oversampling rate of the digital interpolation filter and the delta-sigma modulator is 32 fS, 64 fS, or
128 fS. The total oversampling rate is determined by the desired sampling frequency. If fS ≤ 96 kHz, then the
OVER bit in register 12 can be set to an oversampling rate of 64 fS or 128 fS. If fS > 96 kHz, then the OVER bit
can be used to set the oversampling rate to 32 fS or 64 fS. Figure 37 shows the out-of-band quantization-noise
plots for both the 64× and 128× oversampling scenarios. Notice that the 128× oversampling plot shows
significantly improved out-of-band noise performance, allowing for a simplified low-pass filter to be used at the
output of the DAC.
36
Copyright 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): PCM1602A
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