參數(shù)資料
型號: PCM3002EG
元件分類: Codec
英文描述: 16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS
中文描述: 16/20-BIT單端模擬輸入/輸出立體聲編解碼器
文件頁數(shù): 29/39頁
文件大小: 515K
代理商: PCM3002EG
www.ti.com
PCM3002
PCM3003
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
A[1:0]
Bits 10, 9: Register address
These bits define the address for register 2:
A1
1
A0
0
REGISTER
Register 2
PDAD:
Bit 8: ADC power-down control
This bit places the ADC section in the lowest power-consumption mode. The ADC operation is
stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC
power-down mode enable. Figure 46 illustrates the ADC DOUT response for ADC power-down
ON/OFF. This does not affect the DAC operation.
PDAD
0
1
DAC POWER-DOWN STATUS
Power-down mode disabled (default)
Power-down mode enabled
BYPS:
Bit 7: ADC high-pass filter bypass control
This bit enables or disables the high-pass filter for the ADC.
BYPS
0
1
FILTER BYPASS STATUS
High-pass filter enabled (default)
High-pass filter disabled (bypassed)
PDDA:
Bit 6: DAC power-down control
This bit places the DAC section in the lowest power-consumption mode. The DAC operation is
stopped by cutting the supply current to the DAC section, and VOUT is fixed to GND during DAC
power-down mode enable. Figure 46 illustrates the DAC VOUT response for DAC power-down
ON/OFF. This does not affect the ADC operation.
PDDA
0
1
ADC POWER-DOWN STATUS
Power-down mode disabled (default)
Power-down mode enabled
ATC:
Bit 5: DAC attenuation data mode control
When set to 1, the register 0 attenuation data can be used for both DAC channels. In this case, the
register 1 attenuation data is ignored.
ATC
0
1
ATTENUATION CONTROL
Individual channel attenuation data control (default)
Common channel attenuation data control
IZD:
Bit 4: DAC infinite zero detection and mute control
This bit enables the infinite zero detection circuit in the PCM3002. When enabled, this circuit
disconnects the analog output amplifier from the delta-sigma DAC when the input is continuously
zero for 65,536 consecutive cycles of BCKIN.
IZD
0
1
INFINITE ZERO DETECT STATUS
Infinite zero detection and mute control disabled (default)
Infinite zero detection and mute control enabled
OUT:
Bit 3: DAC output enable control
When set to 1, the outputs are forced to V
/2 (bipolar zero). In this case, all registers in the
PCM3002 hold the present data. Therefore, when set to 0, the outputs return to the previous
programmed state.
OUT
0
1
DAC OUTPUT STATUS
DAC outputs enabled (default normal operation)
DAC outputs disabled (forced to BPZ)
29
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