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參數(shù)資料
| 型號： | PCM3003EG4 |
| 元件分類： | Codec |
| 英文描述： | 16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS |
| 中文描述： | 16/20-BIT單端模擬輸入/輸出立體聲編解碼器 |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 515K |
| 代理商： | PCM3003EG4 |
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BCKIN
LRCIN
DIN
t
(BCH)
t
(BCL)
t
(LRP)
t
(LB)
t
(BCY)
0.5 V
DD
t
(BL)
DOUT
t
(BDO)
t
(LDO)
0.5 V
DD
t
(DIS)
t
(DIH)
0.5 V
DD
0.5 V
DD
T002101
SYSTEM CLOCK
The system clock for the PCM3002/3003 must be either 256 f
S
, 384 f
S
, or 512 f
S
, where f
S
is the audio sampling
frequency. The system clock should be provided at the SYSCLK input (pin 9).
PCM3002
PCM3003
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
BCKIN pulse cycle time
BCKIN pulse duration, HIGH
BCKIN pulse duration, LOW
BCKIN rising edge to LRCIN edge
LRCIN edge to BCKIN rising edge
LRCIN pulse duration
DIN setup time
DIN hold time
DOUT delay time to BCKIN falling edge
DOUT delay time to LRCIN edge
Rising time of all signals
Falling time of all signals
t
(BCY)
t
(BCH)
t
(BCL)
t
(BL)
t
(LB)
t
(LRP)
t
(DIS)
t
(DIH)
t
(BDO)
t
(LDO)
t
(RISE)
t
(FALL)
300 ns (min)
120 ns (min)
120 ns (min)
40 ns (min)
40 ns (min)
t
(BCY)
(min)
40 ns (min)
40 ns (min)
40 ns (max)
40 ns (max)
20 ns (max)
20 ns (max)
Figure 43. Audio Data Input/Output Timing
The PCM3002/3003 also has a system-clock detection circuit that automatically senses if the system clock is
operating at 256 f
S
, 384 f
S
, or 512 f
S
. When a 384-f
S
or 512-f
S
system clock is used, the clock is divided to 256 f
S
automatically. The 256-f
S
clock is used to operate the digital filters and the delta-sigma modulators.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies; Figure 44 illustrates
the system clock timing.
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (MHz)
384 f
s
12.2880
16.9344
18.4320
256 f
s
8.1920
11.2896
12.2880
512 f
s
16.3840
22.5792
24.5760
32
44.1
48
22
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