參數(shù)資料
型號(hào)： PCM3003EG4
元件分類： Codec
英文描述： 16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS
中文描述： 16/20-BIT單端模擬輸入/輸出立體聲編解碼器
文件頁數(shù)： 28/39頁
文件大小： 515K
代理商： PCM3003EG4
www.ti.com
PROGRAM REGISTER 1
res:
Bits 15–11: Reserved
These bits are reserved and should be set to 0.
PROGRAM REGISTER 2
res:
Bits 15–11: Reserved
These bits are reserved and should be set to 0.
PCM3002
PCM3003
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
A[1:0]
Bits 10, 9: Register address
These bits define the address for register 0:
A1
0
A0
0
REGISTER
Register 0
LDL
Bit 8: DAC attenuation data load control for left channel
This bit is used to set analog outputs of the left and right channels simultaneously. The output level
is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new attenuation
data is ignored, and the output level remains at the previous attenuation level. The LDR bit in
register 1 has the equivalent function as LDL. When either LDL or LDR is set to 1, the output levels
of the left and right channels are controlled simultaneously.
AL (7:0)
Bits 7–0: DAC attenuation data for left channel
AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by:
ATT = 20
×
log
10
(AL[7:0]/256) [dB], except AL[7:0] = FFh
ATTENUATION LEVEL
–
∞
dB (mute)
–48.16 dB
:
–0.07 dB
0 dB (default)
AL[7:0]
00h
01h
:
FEh
FFh
A[1:0]
Bits 10, 9: Register address
These bits define the address for register 1:
A1
0
A0
1
REGISTER
Register 1
LDR
Bit 8: DAC attenuation data load control for right channel
This bit is used to set analog outputs of the left and right channels simultaneously. The output level
is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the new
attenuation data is ignored, and the output level remains at the previous attenuation level. The LDL
bit in register 0 has the equivalent function as LDR. When either LDL or LDR is set to 1, the output
levels of the left and right channels are controlled simultaneously.
AR[7:0]
Bits 7–0: DAC attenuation data for right channel
AR7 and AR0 are the MSB and LSB, respectively.
ATT = 20
×
log
10
(AR[7:0]/256) [dB], except AR[7:0] = FFh
ATTENUATION LEVEL
–
∞
dB (mute)
–48.16 dB
:
–0.07 dB
0 dB (default)
AR[7:0]
00h
01h
:
FEh
FFh
28
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