參數(shù)資料
型號: PCM3003EG4
元件分類: Codec
英文描述: 16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS
中文描述: 16/20-BIT單端模擬輸入/輸出立體聲編解碼器
文件頁數(shù): 25/39頁
文件大小: 515K
代理商: PCM3003EG4
www.ti.com
Within 1/f
S
t
(DACDLY2)
(32/f
S
)
V
COM
Normal Data
(0.5 V
CC
)
Undefined
Data
Normal Data
Synchronous
Asynchronous
Synchronous
Resynchronization
Synchronization Lost
DAC V
OUT
State of Synchronization
T0020-03
Normal Data
(1)
Zero Data
Normal Data
ADC DOUT
t
(ADCDLY2)
(32/f
S
)
Undefined
Data
ZERO FLAG OUTPUT: PCM3002 ONLY
Pin 16 is an open-drain output, used as the infinite zero detection flag on the PCM3002 only. When input data is
continuously zero for 65,536 BCKIN cycles, ZFLG is LOW; otherwise, ZFLG is in a high-impedance state.
OPERATIONAL CONTROL
The PCM3002 can be controlled in a software mode with a three-wire serial interface on MC (pin 18),
MD (pin 17), and ML (pin 8). Table 2 indicates selectable functions, and Figure 49 and Figure 50 illustrate the
control data input format and timing. The PCM3003 only allows for control of 16/20-bit data format, digital
de-emphasis, and power-down control by hardware pins.
PCM3002
PCM3003
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
(1)
The HPF transient response (exponentially attenuated signal from
±
0.2% dc of FSR with 200-ms time constant)
appears initially.
Figure 48. DAC Output and ADC Output for Loss of Synchronization
Table 2. Selectable Functions (O = User Selectable; X = Not Available)
FUNCTION
ADC/DAC
ADC/DAC
ADC/DAC
ADC/DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
ADC
DAC
ADC
PCM3002
PCM3003
Audio data format
LRCIN polarity
Loopback control
Left-channel attenuation
Right-channel attenuation
Attenuation control
Infinite zero detection and mute
DAC output control
Soft mute control
De-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz)
ADC power-down control
DAC power-down control
High-pass filter operation
Four selectable formats
O
O
O
O
O
O
O
O
O
O
O
O
Two selectable formats
X
X
X
X
X
X
X
X
O
O
O
X
25
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