SBAS452 鈥� SEPTEMBER 2008 ..........................................." />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PCM3168APAPRG4
寤犲晢锛� Texas Instruments
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 32/68闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC 24-BIT AUDIO CODEC 64-HTQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
椤�(l猫i)鍨嬶細 闊抽牷绶ㄨВ纰煎櫒
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶
鍒嗚鲸鐜囷紙浣嶏級锛� 24 b
ADC / DAC 鏁�(sh霉)閲忥細 6 / 8
涓夎绌嶅垎瑾�(di脿o)璁婏細 鏄�
S/N 姣�锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db)锛� 107 / 112锛堝樊鍒嗭級锛�104 / 112锛堝柈绔級
鍕�(d貌ng)鎱�(t脿i)鑼冨湇锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db)锛� 107 / 112锛堝樊鍒嗭級锛�104 / 112锛堝柈绔級
闆诲 - 闆绘簮锛屾ā鎿細 4.5 V ~ 5.5 V
闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 3 V ~ 3.6 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 64-TQFP 瑁搁湶鐒婄洡(p谩n)
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 64-HTQFP锛�10x10锛�
鍖呰锛� 甯跺嵎 (TR)
REGISTER DEFINITIONS
SBAS452 鈥� SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
64
40
MRST
SRST
鈥�
SRDA1
SRDA0
MRST
Mode control register reset for the ADC and DAC
This bit sets the mode control register reset to the default value. Pop-noise may be generated.
Returning the MRST bit to '1' is unneccesary, because it is automatically set to '1' after the mode
control register is reset.
Default value = 1.
MRST
Mode control register reset
0
Set default value
1
Normal operation (default)
SRST
System reset for the ADC and DAC
This bit controls system reset, the relation between system clock and sampling clock
re-synchronization, and ADC operation and DAC operation restart. The mode control register is
not reset and the PCM3168A and PCM3168A-Q1 do not go into a power-down state. The fade-in
sequence is supported in the resume process, but pop-noise may be generated. Returning the
SRST bit to '1' is unneccesary; it is automatically set to '1' after triggering a system reset.
Default value = 1.
SRST
System reset
0
Resynchronization
1
Normal operation (default)
SRDA[1:0]
DAC Sampling mode select
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is
automatically set according to multiples between the system clock and sampling clock, single rate
for 512 fS and 768 fS, dual rate for 256 fS or 384 fS, and quad rate for 128 fS and 192 fS.
Default value = 00.
SRDA
DAC Sampling mode select
00
Auto (default)
01
Single rate
10
Dual rate
11
Quad rate
38
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3168A PCM3168A-Q1
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-B23-IW-B1 CONVERTER MOD DC/DC 24V 100W
VI-BN1-IY-F3 CONVERTER MOD DC/DC 12V 50W
VI-BWX-IX-B1 CONVERTER MOD DC/DC 5.2V 75W
VE-2NT-CU-S CONVERTER MOD DC/DC 6.5V 200W
VI-B7Z-IW-F2 CONVERTER MOD DC/DC 2V 40W
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
PCM3168A-Q1 鍒堕€犲晢:TI 鍒堕€犲晢鍏ㄧū(ch膿ng):Texas Instruments 鍔熻兘鎻忚堪:24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec with Differential Input/Output
PCM3168ATPAPQ1 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC 24B,6-In/8-Out Audio CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤�(l猫i)鍨�: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤�(l猫i)鍨�:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
PCM3168ATPAPRQ1 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC 24B,6-In/8-Out Audio CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤�(l猫i)鍨�: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤�(l猫i)鍨�:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
PCM3168ATPAPRQ1G4 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC 24B,6-In/8-Out Audio CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤�(l猫i)鍨�: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤�(l猫i)鍨�:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
PCM3168TPAPRQ1 鍒堕€犲晢:Texas Instruments 鍔熻兘鎻忚堪:
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

鎴戠殑鑱�(li谩n)绯绘柟寮�

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