參數(shù)資料
型號: PCM3500DATASHEET
英文描述: PCM3500 Data Sheet - Low Voltage. Low Power. 16-Bit. Mono SoundPlus VOICE
中文描述: PCM3500數(shù)據(jù)表-低電壓。低功耗。 16位。單SoundPlus語音
文件頁數(shù): 16/26頁
文件大小: 199K
代理商: PCM3500DATASHEET
16
PCM3500
SYNCHRONIZATION REQUIREMENTS
The PCM3500 requires that FS and BCK be synchronous
with the system clock. Internal circuitry is included to detect
a loss of synchronization between FS and the system clock
input. If the phase relationship between FS and the system
clock varies more than
±
1.5 BCK periods, the PCM3500
will detect a loss of synchronization. Upon detection, the
DAC output is forced to 0.5V
CC
and the DOUT pin is forced
to a high impedance state. This occurs within one sampling
clock (FS) period of initial detection. Figure 10 shows the
loss of synchronization operation and the DAC and ADC
output delays associated with it.
TIME SLOT OPERATION
The PCM3500 serial interface supports Time Division
Multiplexing (TDM) using the Time Slot Mode. Up to four
PCM3500s may be connected on the same 4-wire serial
interface bus. This is useful for system applications that
require multiple modem or voice channels. Figure 11 shows
examples of Time Slot Mode connections.
Time Slot Mode defines a 64-bit long frame, composed of
four time slots. Each slot is 16 bits long and corresponds to
one of four CODECs. The FS pin on the first PCM3500
(CODEC A, Slot 0) is used as the master frame sync, and
operates at the sampling frequency, f
S
. The bit clock, BCK,
operates at 64f
S
. DIN and DOUT of each CODEC also
operate at 64f
S
. Figure 12 shows the operation of the Time
Slot Mode.
Time Slot operation is enabled or disabled using the TSC
input (pin 7). The state of the TSC pin is updated at power-
on reset, or on the rising edge of PWDN input (if using
external reset or power-down mode). A forced reset is
required when changing from Slave to Master Mode, or visa
versa, in real time.
FIGURE 10. Loss of Synchronization Operation and Timing.
FIGURE 11. Time Slot Mode Connections.
Synchronous
Asynchronous
Synchronization
Lost
Resynchronization
within
1/f
S
Synchronous
Normal
Normal
t
ADCDLY2
(32/f
S
)
t
DACDLY2
(32/f
S
)
V
(0.5 V
CC
)
V
(0.5 V
CC
)
State of
Synchronization
DAC V
OUT
Normal
Normal
(1)
High Impedance
ADC DOUT
NOTE: (1) The HPF transient response (exponentially attenuated signal from
±
0.2% DC of FSR
with 200ms time constant) appears initially.
Undefined Data
Undefined Data
V
DD
V
DD
Controller
GND
V
DD
SCKIO
XTI
XTO
FS
BCK
DIN
DOUT
FSO
M/S
TSC
PCM3500
(CODEC B, Slot 1)
PCM3500
(CODEC A, Slot 0)
To Two PCM3500s
SCKIO
XTI
XTO
FS
BCK
DIN
DOUT
FSO
M/S
TSC
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PCM3500E/2K 功能描述:接口—CODEC Lo-Vlt Lo-Pwr Mono Voice/Modem Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
PCM3500E/2KG4 功能描述:接口—CODEC Lo-Vlt Lo-Pwr Mono Voice/Modem Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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PCM3501 制造商:BB 制造商全稱:BB 功能描述:Low Voltage, Low Power, 16-Bit, Mono VOICE/MODEM CODEC