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參數(shù)資料
| 型號： | PCM4222PFBR |
| 英文描述： | High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter |
| 中文描述： | 高性能，雙通道，24位，216kHz的采樣多位Δ-Σ模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 28/38頁 |
| 文件大?。?/td> | 604K |
| 代理商： | PCM4222PFBR |
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TYPICAL CONNECTIONS
Figure 48
and
Figure 49
provide typical connection diagrams for the PCM4222.
Figure 48
illustrates an
application where both PCM and DSD outputs are available.
Figure 49
illustrates connections for a typical
application using the Multi-Bit Modulator output mode. Both figures show recommended power-supply bypass
and reference filter capacitors. These components should be located as close to the corresponding PCM4222
package pins as physically possible. Larger power-supply bypass capacitors may be placed on the bottom side
of the printed circuit board (PCB). However, reference decoupling capacitors should be located on the top side
of the PCB to avoid issues with added via inductance.
PCM4222
SBAS399A–OCTOBER 2006–REVISED MARCH 2007
Table 11. MBM Mode Pin Mapping vs PCM and DSD Modes
PIN NUMBER
17
18
19
20
21
22
25
26
MBM MODE FUNCTION
MOD1 data output (LSB)
MOD2 data output
MOD3 data output
MOD4 data output
MOD5 data output
MOD6 data output
MCKO master clock output ( f
MCKO
= f
MCKI
)
WCKO word clock output ( f
WCKO
= f
MCKO
÷
2 )
PCM AND DSD MODE FUNCTION
HPFDR
HPFDL
FS0
FS1
DF
DSDEN
SUB1
SUB0
As
Figure 48
illustrates, the audio host device may be a digital signal processor (DSP), digital audio interface
transmitter (DIT), or a programmable logic device. DSD data capture may be accomplished using a
programmable logic device or an audio host capable of capturing/processing the 1-bit data.
In
Figure 49
, the modulator output may be connected to a programmable logic device that is configured to
perform digital decimation filtering and post-processing tasks.
28
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