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參數(shù)資料
| 型號： | PCM4222PFBR |
| 英文描述： | High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter |
| 中文描述： | 高性能，雙通道，24位，216kHz的采樣多位Δ-Σ模擬到數(shù)字轉換器 |
| 文件頁數(shù)： | 34/38頁 |
| 文件大?。?/td> | 604K |
| 代理商： | PCM4222PFBR |
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PCM4222
Divided by 2
MCKI
BCK
LRCK
DIX4192
or
SRC4392
512f (Normal)
256f (Double Speed)
128f (Quad Speed)
Master
Clock
MCLK
DATA
BCKA
LRCKA
SDINA
PCM4222
SBAS399A–OCTOBER 2006–REVISED MARCH 2007
VDDPCM4222 = VIODIX4192 or SRC4392.
Audio data format if I
2
S or Left Justified.
Interface supports ADC Slave or Master configurations, depending on DIX4192, SRC4382, or SRC4392 register
setup.
Figure 54. Interfacing the PCM4222 to a
DIT4192
,
SRC4382
, or
SRC4392
Table 12. Register Configuration Sequence for an ADC Master Mode Interface
REGISTER ADDRESS (hex)
7F
REGISTER DATA (hex)
00
00
01
00
64
24
04
00
COMMENTS
Select Register Page 0
Port A is Slave mode with Left-Justified audio data format, or
Port A is Slave mode with I
2
S Data format
Default for Port A Slave mode operation
Divide MCLK by 512 for Normal sampling,or
Divide MCLK by 256 for Double Speed Sampling, or
Divide MCLK by 128 for Quad Speed sampling
Line Driver and AESOUT buffer enabled
Data buffers on Register Page 2 are the source for the DIT
channel status (C) and user (U) data
Power up Port A and the DIT
03
04
07
08
09
01
01
34
Table 13. Register Configuration Sequence for an ADC Slave Mode Interface
REGISTER ADDRESS (hex)
7F
REGISTER DATA (hex)
00
08
09
03
01
00
64
24
04
00
COMMENTS
Select Register Page 0
Port A is Master mode with Left-Justified audio data format, or
Port A is Master mode with I
2
S Data format
Divide MCLK by 512 for Normal sampling, or
Divide MCLK by 256 for Double Speed sampling, or
Divide MCLK by 128 for Quad Speed sampling
Divide MCLK by 512 for Normal sampling,or
Divide MCLK by 256 for Double Speed Sampling, or
Divide MCLK by 128 for Quad Speed sampling
Line Driver and AESOUT buffer enabled
Data buffers on Register Page 2 are the source for the DIT
channel status (C) and user (U) data
Power up Port A and the DIT
03
04
07
08
09
01
01
34
34
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