參數(shù)資料
型號(hào): PDI1394L21
廠商: NXP Semiconductors N.V.
英文描述: Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
中文描述: 全雙工鏈路層Ccontroller影音(全雙工視聽(tīng)鏈接層控制器)
文件頁(yè)數(shù): 41/54頁(yè)
文件大?。?/td> 242K
代理商: PDI1394L21
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
41
13.3
Asynchronous Control and Status Interface
13.3.1
Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
D
A
A
A
SV00889
MAXRC
TOS
TOF
3130
Reset Value 0x00300320
Bit 23:
Bit 22:
Bit 21:
Bit 20:
R/W
R/W
R/W
R/W
DIS_BCAST: Disable the reception of broadcast packets.
ARXRST: Asynchronous receiver reset. This bit will auto clear when the link layer state machine is idle.
ATXRST: Asynchronous transmitter reset
ARXALL: Receive and filter only RESPONSE packets. When set (1), all responses are stored. When clear (0), only
solicited responses are stored.
MAXRC: Maximum number of asynchronous transmitter single phase retries
TOS: Time out seconds, integer of 1 second of the split transaction time out timer. Resets to “000”. This timer is set
to the maximum amount of time the transmitter will wait for a pending response before the transmitter will begin
transmitting the next available request packet. Also see TOF bits of this timer.
TOF: Time out fractions, integer of 1/8000 second. Resets to 0320h, which is 100 milliseconds. During the timeout of
the split transaction timer, subsequent split transactions are blocked. If it is desired to transmit multiple split
transactions this can be accomplished by following this procedure: (1) set the split transaction timer value to “0”, (2)
disable the split time–out interrupt (TIMEOUT, bit 7 in register 0x0A0); (3) clear (set to “0”) the unsolicited response
filter bit (ARXALL, bit 20 in register 0x080). Now use tLabels (transaction Labels, see section 12.5.1) to pair
transmitted packets with received packets. Use software timers to time–out the subsequent pending responses.
Bit 19..16:
Bit 15..13:
R/W
R/W
Bit 12..0:
R/W
13.3.2
Asynchronous RX/TX Memory Status (ASYMEM) – Base Address: 0x084
T
R
T
T
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
T
T
R
R
R
R
R
R
T
R
T
T
T
3130
SV00918
T
Reset Value 0x00033333
Unused bits read ‘0’. The information in this register is primarily used for diagnostics.
TRSPQIDLE: Transmitter response queue is idle. Indicates that the transfer register for this queue is empty.
TREQQIDLE: Transmitter request queue is idle. Indicates that the transfer register for this queue is empty.
RRSPQF: Receiver response queue full.
RRSPQAF: Receiver response queue almost full (precisely 1 more quadlet available).
RRSPQ5AV: Receiver response queue at least 5 quadlets available.
RRSPQE: Receiver response queue empty.
RREQQF: Receiver request queue full.
RREQQAF: Receiver request queue almost full (precisely 1 more quadlet available).
RREQQ5AV: Receiver request queue at least 5 quadlets available.
RREQQE: Receiver request queue empty.
TRSPQF: Transmitter response queue full.
TRSPQAF: Transmitter response queue almost full (precisely 1 more quadlet available).
TRSPQ5AV: Transmitter response queue at least 5 quadlets available.
TRSPQE: Transmitter response queue empty.
TREQQF: Transmitter request queue full.
TREQQAF: Transmitter request queue almost full (precisely 1 more quadlet available).
TREQQ5AV: Transmitter request queue at least 5 quadlets available.
TREQQE: Transmitter request queue empty.
Bit 17:
Bit 16:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bit 10:
Bit 9:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
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