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參數(shù)資料
| 型號： | PDM41532LA15T |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO44 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 368K |
| 代理商： | PDM41532LA15T |
Rev. 1.3 - 4/10/98
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PRELIMINARY
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Description
The PDM41532 is a high-performance CMOS static
RAM organized as 65,536 x 16 bits. The PDM41532
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM41532 operates from a single 5.0V power
supply and all inputs and outputs are fully TTL-
compatible. The PDM41532 comes in two versions,
the standard power version PDM41532SA and a low
power version PDM41532LA. The two versions are
functionally the same and only differ in their power
consumption.
The PDM41532 is available in a 44-pin 400 mil plas-
tic SOJ and a 44-pin plastic TSOP (II) package
suitable for high-density surface assembly and is
suitable for use in high-speed applications such as
cache memory and high-speed storage.
PDM41532
64K x 16 CMOS
Static RAM
A8-A0
Memory
Cell
Array
256 x 128 x 32
Row
Address
Buffer
Control
Logic
Sense Amp
Column
Decoder
Column
Address
Buffer
Row
Decoder
Clock
Generator
A15-A9
CE
LB
UB
OE
WE
Data
Input/
Output
Buffer
Vcc
Vss
I/O15-I/O0
Features
n High-speed access times
- Com’l: 10, 12, 15 and 20 ns
- Ind: 12, 15 and 20 ns
n Low power operation (typical)
- PDM41532SA
Active: 350 mW
Standby: 50 mW
- PDM41532LA
Active: 300 mW
Standby: 25mW
n High-density 64K x 16 architecture
n Single +5V (±10%) power supply
n Fully static operation
n TTL-compatible inputs and outputs
n Output buffer controls: OE
n Data byte controls: LB, UB
n Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
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