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參數(shù)資料
| 型號(hào)： | PE3239-11 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2.2 GHz Integer-N PLL for Low Phase Noise Applications |
| 中文描述： | 2.2 GHz的整數(shù)N的低相位噪聲鎖相環(huán)的應(yīng)用 |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大?。?/td> | 221K |
| 代理商： | PE3239-11 |
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PE3239
Product Specification
Enhancement Register
Copyright
Peregrine Semiconductor Corp. 2001
Page 10 of 13
File No. 70/0047~01A
|
UTSi
CMOS RFIC SOLUTIONS
R
C1
C2
Charge
Pump
To VCO
Tune
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
f
p
output
Drives the M counter output onto the Dout output.
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
f
c
output
Drives the reference counter output onto the Dout output
Bit 7
Reserved**
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (f
p
) and the reference
counter (f
c
). It has two outputs, namely PD_
U
, and
PD_
D
. If the divided VCO leads the divided
reference in phase or frequency (f
p
leads f
c
), PD_
D
pulses “l(fā)ow”. If the divided reference leads the
divided VCO in phase or frequency (f
c
leads f
p
),
PD_
U
pulses “l(fā)ow”. The width of either pulse is
directly proportional to phase offset between the
two input signals, f
p
and f
c
.
The signals from the phase detector couple directly
to a charge pump. PD_
U
controls a current source
at pin CP with constant amplitude and pulse
duration approximately the same as PD_
U
. PD_
D
similarly drives a current sink at pin CP. The
current pulses from pin CP are low pass filtered
externally and then connected to the VCO tune
voltage. PD_
U
pulses result in a current source,
which increases the VCO frequency and PD_
D
results in a current sink, which decreases VCO
frequency when using a positive Kv VCO.
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_
U
and
PD_
D
waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_
U
and PD_
D
.
Figure 7. Typical PE3239 Loop Filter Application Example
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PE3239-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.2 GHz Integer-N PLL for Low Phase Noise Applications |
| PE3239EK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.2 GHz Integer-N PLL for Low Phase Noise Applications |
| PE3240 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:2.2 GHz UltraCMOS? Integer-N PLL for Low Phase Noise Applications |
| PE3240EK | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:2.2 GHz UltraCMOS? Integer-N PLL for Low Phase Noise Applications |
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