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參數(shù)資料
| 型號： | PE3239-11 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2.2 GHz Integer-N PLL for Low Phase Noise Applications |
| 中文描述： | 2.2 GHz的整數(shù)N的低相位噪聲鎖相環(huán)的應用 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 221K |
| 代理商： | PE3239-11 |
PE3239
Product Specification
Figure 2. Pin Configuration
Copyright
Peregrine Semiconductor Corp. 2001
Page 2 of 13
File No. 70/0047~01A
|
UTSi
CMOS RFIC SOLUTIONS
Table 1. Pin Descriptions
Pin No.
Pin Name
Type
Description
1
V
DD
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
2
Enh
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 k
pull-up
resistor.
3
S_WR
Input
Serial load enable input. While S_WR is “l(fā)ow”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
4
Sdata
Input
Binary serial data input. Input data entered MSB first.
5
Sclk
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “l(fā)ow”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
6
GND
Ground.
7
FSELS
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 k
pull-down resistor.
8
E_WR
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement
register on the rising edge of Sclk. Internal 70 k
pull-down resistor.
9
V
DD
(Note 1)
Same as pin 1.
10
F
in
Input
Prescaler input from the VCO. Max frequency input is 2.2 GHz.
11
F
in
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50
resistor to the ground plane.
12
GND
Ground.
13
Cext
Output
Logical “NAND” of PD_
U
and PD_
D
terminated through an on chip, 2 k
series resistor. Connecting Cext to an
external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
14
LD
Output
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
15
Dout
Output
Data out function, Dout, enabled in enhancement mode.
16
V
DD
(Note 1)
Same as pin 1.
V
DD
1
ENH
2
S_WR
3
Sdata
4
Sclk
5
GND
6
FSELS
7
E_WR
8
V
DD
9
F
in
10
F
in
11
GND
12
Cext
13
LD
14
Dout
15
V
DD
16
CP
17
N/C
18
GND
19
f
r
20
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