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參數(shù)資料
| 型號(hào)： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分?jǐn)?shù)N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | PE3293 |
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 18
Product Description
PLLs. The 32/33 RF prescaler (PLL1) operates up to 1.8
GHz and the 16/17 IF prescaler (PLL2) operates up to
550 MHz.
Applications
Triple mode,dual-band PCS / Cellular handset
PCS/CDMA/Cellular handsets
PCS/CDMA/Cellular base stations
Figure 1. Block Diagram
PRODUCT SPECIFICATION
PE3293
1.8 GHz / 550 MHz Dual
Fractional-N Ultra-Low
Spurious PLL for Frequency
Synthesis
Features
Industry leading fractional spur
compensation: no adjusting
required, stable over temp.
Ultra-Low Power consumption:
4.0 mA typical, both loops
operating
Modulo-32 fractional-N main
counters
Supply voltage range 2.7 to 3.3
VDC
The PE3293 is a dual fractional-N phase-lock loop (PLL)
IC designed for frequency synthesis and fabricated on
Peregrine’s patented UTSi CMOS process. Each PLL
includes a prescaler, phase detector, charge pump and
on-board fractional spur compensation.
The patented spur compensation circuitry designed into
the device ensures superior spur performance over the
full temperature and VCO tuning range.
The PE3293 provides fractional-N division with power-of-
two denominator values up to 32. This allows
comparison frequencies up to 32 times the channel
spacing, providing a lower phase noise floor than integer
32/33
Prescaler
f
in
1
19-bit Fractional-N
Main Divider
Fractional Spur
Compensation
Fractional Spur
Compensation
18-bit Fractional-N
Main Divider
9-bit Reference
Divider
9-bit Reference
Divider
21-bit Serial Control
Interface
Ref.
Amp.
f
r
Clock
Data
LE
f
in
2
16/17
Prescaler
f
o
LD
CP1
CP2
Phase
Detector
Phase
Detector
Charge
Pump
Charge
Pump
Multiplexer
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