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參數(shù)資料
| 型號： | PE97632ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| 中文描述： | 3.2 GHz的Δ-Σ調(diào)制的低相位噪聲應(yīng)用分?jǐn)?shù)N頻率合成器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 373K |
| 代理商： | PE97632ES |
Advance Information
PE97632
Page 10 of 16
2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0205-02
│
UltraCMOS RFIC Solutions
While the E_WR input is “high” and the S_WR in-
put is “l(fā)ow”, serial input data (Sdata input), B
0
to
B
7
, are clocked serially into the enhancement reg-
ister on the rising edge of Sclk, MSB (B
0
) first. The
enhancement register is double buffered to pre-
vent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR ac-
cording to the timing diagram shown in Figure 4.
After the falling edge of E_WR, the data provide
control bits as shown in Table 9 on page 10 will
have their bit functionality enabled by asserting
the
Enh
input “l(fā)ow”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
“Direct” input “high”.
Counter control bits are set directly at the pins as
shown in Table 7 and Table 8.
Table 7. Secondary Register Programming
Interface
Mode
Direct
Table 8. Auxiliary Register Programming
Interface
Mode
Direct
Table 9. Enhancement Register Programming
Interface
Mode
Enh
R
5
R
4
M
8
M
7
Pre_en
M
6
M
5
M
4
M
3
M
2
M
1
M
0
R
3
R
2
R
1
R
0
A
3
A
2
A
1
A
0
Addr
1
R
5
R
4
M
8
M
7
Pre_en
M
6
M
5
M
4
M
3
M
2
M
1
M
0
R
3
R
2
R
1
R
0
A
3
A
2
A
1
A
0
X
Serial*
1
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
B
11
B
12
B
13
B
14
B
15
B
16
B
17
B
18
B
19
0
*Serial data clocked serially on Sclk rising edge while E_WR “l(fā)ow” and captured in secondary register on S_WR rising edge.
Enh
K
17
K
16
K
15
K
14
K
13
K
12
K
11
K
10
K
9
K
8
K
7
K
6
K
5
K
4
K
3
K
2
K
1
K
0
Rsrv
Rsrv
Addr
1
K
17
K
16
K
15
K
14
K
13
K
12
K
11
K
10
K
9
K
8
K
7
K
6
K
5
K
4
K
3
K
2
K
1
K
0
X
X
X
Serial*
1
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
B
11
B
12
B
13
B
14
B
15
B
16
B
17
B
18
B
19
1
*Serial data clocked serially on Sclk rising edge while E_WR “l(fā)ow” and captured in secondary register on S_WR rising edge.
Enh
Reserved
Reserved
f
p
output
Power
Down
Counter
load
MSEL
output
f
c
output
LD Disable
Serial*
0
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge
.
MSB (first in)
MSB (first in)
(last in) LSB
(last in) LSB
(last in) LSB
MSB (first in)
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