參數(shù)資料
型號: PE97632ES
廠商: Electronic Theatre Controls, Inc.
英文描述: 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications
中文描述: 3.2 GHz的Δ-Σ調(diào)制的低相位噪聲應用分數(shù)N頻率合成器
文件頁數(shù): 11/16頁
文件大?。?/td> 373K
代理商: PE97632ES
Advance Information
PE97632
Page 11 of 16
Document No. 70-0205-02
www.psemi.com
2006 Peregrine Semiconductor Corp. All rights reserved.
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Figure 4. Serial Interface Mode Timing Diagram
t
DHLD
t
DSU
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
t
EC
t
CE
E_WR
Sdata
Sclk
S_WR
Table 10. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserve **
Reserved.
Bit 1
Reserve **
Reserved.
Bit 2
f
p
output
Drives the M counter output onto the Dout output.
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
f
c
output
Drives the reference counter output onto the Dout output.
Bit 7
LD Disable
Disables the LD pin for quieter operation.
** Program to 0
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