參數資料
型號： PEF2466-H
元件分類： Codec
英文描述： A-Law/u-Law CODEC
中文描述： A-Law/u-Law編解碼器
文件頁數： 15/73頁
文件大?。?/td> 1618K
代理商： PEF2466-H
PEB 2466
PEF 2466
Pin Descriptions
Hardware Reference Manual
6
2001-02-20
2.2
Pin Definitions and Functions
Table 1
Pin Definitions and Functions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Symbol
SI3_1
SI3_0
SB3_2
SB3_1
SB3_0
SO3_1
SO3_0
SO4_0
SO4_1
SB4_0
SB4_1
SB4_2
SI4_0
SI4_1
Type Function
I
Signaling Input, Channel 3
Pin 1
I
Signaling Input, Channel 3
Pin 0
I/O
Bi-directional Signaling, Channel 3 Pin 2
I/O
Bi-directional Signaling, Channel 3 Pin 1
I/O
Bi-directional Signaling, Channel 3 Pin 0
O
Signaling Output, Channel 3 Pin 1
O
Signaling Output, Channel 3 Pin 0
O
Signaling Output, Channel 4 Pin 0
O
Signaling Output, Channel 4 Pin 1
I/O
Bi-directional Signaling, Channel 4 Pin 0
I/O
Bi-directional Signaling, Channel 4 Pin 1
I/O
Bi-directional Signaling, Channel 4 Pin 2
I
Signaling Input, Channel 4
Pin 0
I
Signaling Input, Channel 4
Pin 1
Interrupt Output Channels 3 and 4
Active high.
Chopper Clock Output 2
Provides 256, 512, or 16384 kHz signal; sync. to MCLK.
Chip Select
Microcontroller Interface chip select, enable to read or
write; active low
Data Clock
Microcontroller Interface data clock, shifts data from or to
device; maximum clock rate 8192 kHz.
Data Input
Microcontroller Interface control data input pin; DCLK
determines data rate.
Data Output
Microcontroller Interface control data output pin; DCLK
determines data rate: DOUT is high impedance "Z" if no
data is transmitted from the SICOFI
4-μC.
Ch.
3
3
3
3
3
3
3
4
4
4
4
4
4
4
15
INT34
O
3, 4
16
CHCLK2
O
all
17
CS#
I
all
18
DCLK
I
all
19
DIN
I
all
20
DOUT
O
all
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