參數(shù)資料
型號： PEF2466-H
元件分類： Codec
英文描述： A-Law/u-Law CODEC
中文描述： A-Law/u-Law編解碼器
文件頁數(shù)： 43/73頁
文件大小： 1618K
代理商： PEF2466-H
PEB 2466
PEF 2466
Interface Description
Hardware Reference Manual
34
2001-02-20
Table 24
Signaling Interface: Pins and Functions for SLIC Interfaces
5.3.2
Debouncing Functions and Interrupt Generation
All signaling inputs are sampled at programmable intervals (Field N in register XR4). If
all the inputs assigned to one channel-pair (1&2 or 3&4) have been stable for two
subsequent samples their values are stored in the signaling registers and the associated
interrupt output (INT12 or INT34) is set high. Refer to the
Programmer’s Reference
Manual
for further details on this function.
5.3.3
Clock Output Signals
Two programmable Chopper Clock Output signals are provided by the PEB 2466:
CHCLK1 (Pin 33) is configured in register XR4.Field T (bits XR4.3 to XR4.0)
CHCLK2 (Pin 16) is configured in register XR5.CHCLK2 (bits XR5.3 and XR5.2)
Both Chopper Clock Output signals are only available if a valid Master Clock signal is
applied to pin MCLK.
CHCLK2 = 16,384 kHz: Requires at least one channel in POWER-UP state.
Symbol
Pin
Function
Ch1
36
35
41
40
39
38
37
Ch2
47
48
42
43
44
45
46
Ch3
2
1
7
6
5
4
3
Ch4
13
14
8
9
10
11
12
SIx_0
SIx_1
SOx_0
SOx_1
SBx_0
SBx_1
SBx_2
INT12
INT34
Signaling Input Channel x, Pin 0.
Signaling Input Channel x, Pin 1.
Signaling Output, Channel x, Pin 0.
Signaling Output, Channel x, Pin 1.
Bi-directional Signaling, Channel x, Pin 0.
Bi-directional Signaling, Channel x, Pin 1.
Bi-directional Signaling, Channel x, Pin 2.
Interrupt Output, Channels 1+2, active high.
Interrupt Output, Channels 3+4, active high.
34
-
-
15
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