參數(shù)資料
型號: PI6C102
廠商: Pericom Semiconductor Corp.
英文描述: Precision Clock Synthesizer for Mobile PCs
中文描述: 精密時鐘合成器移動PC
文件頁數(shù): 3/11頁
文件大?。?/td> 588K
代理商: PI6C102
3
PS8164A 09/29/00
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Power Management Timing
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Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
CPU_STOP# is an input signal used to turn off the CPU clocks for
low power operation. CPU_STOP# is asserted asynchronously by
the external clock control logic with the rising edge of free running
PCI clock and is internally synchronized to the external PCICLK_F
output. All other clocks continue to run while the CPU clocks are
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.
4. ON/OFF latency shown in the diagram is 2 CPU clocks.
5. All other clocks continue to run undisturbed.
6. PWR_DWN# and PCI_STOP# are shown in a HIGH state.
7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
disabled. The CPU clocks are always stopped in a LOW state and
started guaranteeing that the high pulse width is a full pulse. CPU
clock on latency is 2 or 3 CPU clocks and CPU clock off latency
is 2 or 3 CPU clocks.
CPUCLK
(Internal)
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
(External)
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