參數(shù)資料
型號(hào): PI6C102H
廠商: Pericom Semiconductor Corp.
英文描述: DIP Socket; No. of Contacts:16; Pitch Spacing:0.1"; Row Spacing:0.3"; Terminal Type:PCB; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述: 精密時(shí)鐘合成器移動(dòng)PC
文件頁(yè)數(shù): 1/11頁(yè)
文件大小: 588K
代理商: PI6C102H
1
PS8164A 09/29/00
for Mobile PCs
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PCICLK_F
VSSPCI0
PCICLK1
PCICLK3
VDDPCI0
PCICLK2
VDDPCI1
PCICLK4
PCICLK5
VSSPCI1
VSSCORE0
VSSREF
REF
VDDCPU
CPUCLK1
VSSCPU
VDDCORE1
VSSCORE1
PCISTOP#
CPUSTOP#
PWRDWN#
SEL
SEL100/66#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTAL_IN
XTAL_OUT
CPUCLK0
VDDREF
VDDCORE0
Pin Configuration
Block Diagram
Features
Two copies of CPU clock with V
DD
of 2.5V ±5%
100 MHz or 66.6 MHz operation
Six copies of PCI clock, (synchronous with CPU clock) 3.3V
One copy of Ref. Clock @ 14.31818 MHz (3.3V
TTL
)
Low cost 14.31818 MHz crystal oscillator input
Power management control
Isolated core V
DD
, V
SS
pins for noise reduction
28-pin SSOP package (H)
Description
The PI6C102 is a high-speed low-noise clock generator designed
to work with the Pericom's PI6C18x clock buffer to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard 8-X.
Power sequencing of the 3.3V and 2.5V supplies is not required.
An asynchronous PWRDWN# signal may be used to orderly power
down (or up) the system.
28-Pin
H
REF
PCICLK
[1:5]
CPUCLK
[0:1]
REF
OSC
CPUSTOP#
Buffers
2
5
PCICLK_F
PCISTOP#
DIV
XTAL_OUT
XTAL_IN
V
DDREF
V
DDCPU
V
DDCPU
0,1
SEL100/66#
SEL
PWRDWN#
PLL1
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