參數(shù)資料
型號： PI7C8150BMAIE
廠商： Pericom
文件頁數(shù)： 65/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 208-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-FQFP（28x28）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 59 of 109
April 2009 – Revision 1.08
P_PERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
1
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
1 / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
1 / x
0
2
Delayed Write
Downstream
Secondary
1 / 1
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 6-6 shows assertion of S_PERR_L that is set under the following conditions:
PI7C8150B is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C8150B detects a data parity error on the secondary bus or detects P_PERR_L
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
Table 6-6. Assertion of S_PERR_L
S_PERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
0 (asserted)
Read
Downstream
Secondary
x / 1
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / 1
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
0
2
Delayed Write
Upstream
Primary
1 / 1
0
Delayed Write
Upstream
Secondary
x / 1
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 6-7 shows assertion of P_SERR_L. This signal is set under the following conditions:
PI7C8150B has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
PI7C8150B did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
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參數(shù)描述
PI7C8150BMAIE-33 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BND 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BND-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BNDE 功能描述:外圍驅(qū)動器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BNDI 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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