參數(shù)資料
型號： PIC10F222-E/OT
廠商： Microchip Technology
文件頁數(shù)： 52/86頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 512X12 SOT-23-6
標(biāo)準(zhǔn)包裝： 3,000
系列： PIC® 10F
核心處理器： PIC
芯體尺寸： 8-位
速度： 8MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 4
程序存儲(chǔ)器容量： 768B（512 x 12）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 23 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： SOT-23-6
包裝： 散裝
PIC10F220/222
DS41270E-page 54
2007 Microchip Technology Inc.
10.2
DC Characteristics: PIC10F220/222 (Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40×C TA +125×C (extended)
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
V
D002
VDR
RAM Data Retention Voltage(2)
1.5*
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage
to ensure Power-on Reset
—Vss
—
V
IDD
Supply Current(3)
D010
—
175
0.625
250
0.800
275
1.1
400
1.5
μA
mA
μA
mA
VDD = 2.0V, Fosc = 4 MHz
VDD = 5.0V, Fosc = 4 MHz
VDD = 2.0V, Fosc = 8 MHz
VDD = 5.0V, Fosc = 8 MHz
IPD
Power-down Current(4)
D020
—
0.1
1
9
15
μA
VDD = 2.0V
VDD = 5.0V
IWDT
WDT Current(4)
D022
—
1.0
7
18
22
μA
VDD = 2.0V
VDD = 5.0V
*
These parameters are characterized but not tested.
Note
1:
Data in the Typical (“Typ”) column is based on characterization results at 25
°C. This data is for design guidance only
and is not tested.
2:
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3:
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus
rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode.
4:
Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD
or VSS. The peripheral current is the sum of the base IPD and the additional current consumed when the peripheral is
enabled.
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