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參數(shù)資料
| 型號(hào)： | PIC12CE674/JW |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 61/129頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EPROM 2KX14 A/D&EE 8CDIP |
| 標(biāo)準(zhǔn)包裝： | 56 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 10MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲(chǔ)器容量： | 3.5KB（2K x 14） |
| 程序存儲(chǔ)器類型： | EPROM，UV |
| EEPROM 大?。?/td> | 16 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-CDIP（0.300"，7.62mm）窗口 |
| 包裝： | 管件 |
| 配用： | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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1999 Microchip Technology Inc.
DS30561B-page 37
PIC12C67X
6.5
Read Operations
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations; current address read, random
read and sequential read.
6.5.1
CURRENT ADDRESS READ
The EEPROM contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the EEPROM address with the R/W bit set to
one, the EEPROM issues an acknowledge and trans-
mits the 8-bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
6.5.2
RANDOM READ
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
EEPROM as part of a write operation. After the word
address is sent, the processor generates a start condi-
tion following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again, but with the R/W bit set to a one. The
EEPROM will then issue an acknowledge and trans-
mits the 8-bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-9). After this command, the internal address
counter will point to the address location following the
one that was just read.
6.5.3
SEQUENTIAL READ
Sequential reads are initiated in the same way as a ran-
dom read, except that after the device transmits the first
data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-10).
To provide sequential reads, the EEPROM contains an
internal address pointer, which is incremented by one
at the completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
FIGURE 6-8:
CURRENT ADDRESS READ
FIGURE 6-9:
RANDOM READ
FIGURE 6-10: SEQUENTIAL READ
SDA LINE
P
S
T
O
P
CONTROL
BYTE
S
T
A
R
T
DATA
A
C
K
N
O
A
C
K
11
00 X X X 1
X = Don’t Care Bit
ACTIVITY
P
SDA LINE
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
XX X X
S1
1
00 X X X 0
S1
1
00 X X X 1
X = Don’t Care Bit
ACTIVITY
P
SDA LINE
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA n
DATA n + 1
DATA n + 2
DATA n + X
A
C
K
A
C
K
A
C
K
ACTIVITY
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