參數(shù)資料
型號: PIC12F510-I/MC
廠商: Microchip Technology
文件頁數(shù): 27/39頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 1024X12 8DFN
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 150
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: 閃存
RAM 容量: 38 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VFDFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC164334-ND - MODULE SOCKET FOR 8L 2X3MM DFN
AC163022-ND - ADAPTER UNIVERSAL PROG PIC12F5XX
AC162070-ND - HEADER INTRFC MPLAB ICD2 8/14P
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
33
6462AS–ATARM–03-Jun-09
AT91SAM9G10
10.7
Serial Peripheral Interface
Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to
fifteen peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
10.8
Two-wire Interface
Compatibility with standard two-wire serial memories
One, two or three bytes for slave address
Sequential read/write operations
Supports either master or slave modes
Master, multi-master and slave mode operation
Bit rate: up to 400 Kbits
General call supported in slave mode
10.9
USART
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By-8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
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