參數(shù)資料
型號： PIC12F510-I/MC
廠商： Microchip Technology
文件頁數(shù)： 9/39頁
文件大小： 0K
描述： IC PIC MCU FLASH 1024X12 8DFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準包裝： 150
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 8MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 5
程序存儲器容量： 1.5KB（1K x 12）
程序存儲器類型： 閃存
RAM 容量： 38 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VFDFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁面： 637 (CN2011-ZH PDF)
配用： AC164334-ND - MODULE SOCKET FOR 8L 2X3MM DFN
AC163022-ND - ADAPTER UNIVERSAL PROG PIC12F5XX
AC162070-ND - HEADER INTRFC MPLAB ICD2 8/14P
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
17
6462AS–ATARM–03-Jun-09
AT91SAM9G10
8.1.1
Internal Memory Mapping
Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the BMS state at reset.
Note:
1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC
Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
8.1.1.1
Internal SRAM
The AT91SAM9G10 embeds a high-speed 16-Kbyte SRAM.
8.1.1.2
Internal ROM
The AT91SAM9G10 integrates a 32-Kbyte Internal ROM mapped at address 0x0040 0000. It is
also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset.
8.1.1.3
USB Host Port
The AT91SAM9G10 integrates a USB Host Port Open Host Controller Interface (OHCI). The
registers of this interface are directly accessible on the AHB Bus and are mapped like a standard
internal memory at address 0x0050 0000.
8.1.1.4
LCD Controller
The AT91SAM9G10 integrates an LCD Controller. The interface is directly accessible on the
AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.
8.1.2
Boot Strategies
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted for each Master of the Bus Matrix. Refer to the
Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 15.
The AT91SAM9G10 Bus Matrix manages a boot memory that depends on the level on the BMS
pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
Table 8-3.
Internal Memory Mapping
Address
Master 0: ARM926 Instruction
Master 1: ARM926 Data
REMAP(RCB0) = 0
REMAP (RCB0) = 1
REMAP (RCB1) = 0
REMAP (RCB1) = 1
BMS = 1
BMS = 0
BMS = 1
BMS = 0
0x0000 0000
Int. ROM
Int. RAM C
Int. ROM
EBI NCS0(1)
Int. RAM C
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