參數(shù)資料
型號: PIC12F519-I/MS
廠商: Microchip Technology
文件頁數(shù): 49/96頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 1KX12 8MSOP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 100
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: 閃存
RAM 容量: 41 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14
AC164325-ND - MODULE SKT FOR 8MSOP
2008 Microchip Technology Inc.
DS41319B-page 51
PIC12F519
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(W) + (f)
→ (dest)
Status Affected: C, DC, Z
Description:
Add the contents of the W register
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
ANDLW
AND literal with W
Syntax:
[ label ] ANDLW
k
Operands:
0
≤ k ≤ 255
Operation:
(W).AND. (k)
→ (W)
Status Affected: Z
Description:
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(W) .AND. (f)
→ (dest)
Status Affected: Z
Description:
The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
BCF
Bit Clear f
Syntax:
[ label ] BCF
f,b
Operands:
0
≤ f ≤ 31
0
≤ b ≤ 7
Operation:
0
→ (f<b>)
Status Affected: None
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0
≤ f ≤ 31
0
≤ b ≤ 7
Operation:
1
→ (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0
≤ f ≤ 31
0
≤ b ≤ 7
Operation:
skip if (f<b>) = 0
Status Affected: None
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a two-cycle instruction.
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