參數(shù)資料
型號: PIC12F519-I/MS
廠商: Microchip Technology
文件頁數(shù): 50/96頁
文件大小: 0K
描述: IC PIC MCU FLASH 1KX12 8MSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 100
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: 閃存
RAM 容量: 41 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14
AC164325-ND - MODULE SKT FOR 8MSOP
PIC12F519
DS41319B-page 52
2008 Microchip Technology Inc.
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
Operands:
0
≤ f ≤ 31
0
≤ b < 7
Operation:
skip if (f<b>) = 1
Status Affected: None
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
CALL
Subroutine Call
Syntax:
[ label ] CALL k
Operands:
0
≤ k ≤ 255
Operation:
(PC) + 1
→ Top-of-Stack;
k
→ PC<7:0>;
(STATUS<6:5>)
→ PC<10:9>;
0
→ PC<8>
Status Affected: None
Description:
Subroutine call. First, return
address (PC + 1) is pushed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS<6:5>, PC<8> is cleared.
CALL
is a two-cycle instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF f
Operands:
0
≤ f ≤ 31
Operation:
00h
→ (f);
1
→ Z
Status Affected: Z
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h
→ (W);
1
→ Z
Status Affected: Z
Description:
The W register is cleared. Zero bit
(Z) is set.
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h
→ WDT;
0
→ WDT prescaler (if assigned);
1
→ TO;
1
→ PD
Status Affected: TO, PD
Description:
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
COMF
Complement f
Syntax:
[ label ] COMF f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f)
→ (dest)
Status Affected: Z
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
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