參數(shù)資料
型號(hào)： PIC12F635T-I/SN
廠商： Microchip Technology
文件頁(yè)數(shù)： 42/74頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH 1KX14 8SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 3,300
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 帶卷 (TR)
配用： AC162057-ND - MPLAB ICD 2 HEADER 14DIP
Micrel, Inc.
KSZ8841-PMQL
October 2007
47
M9999-100407-1.5
Bit
Default
R/W
Description
A “1” indicates that the function requires a device specific initialization
sequence following transition to the D0 uninitialization state.
The value of this bit is loaded from the PME_DSI bit in the EEPROM
0X6 word.
4
0
RO
Reserved
3
0
RO
PME Clock
When this bit is a “1”, it indicates that the function relies on the
presence of the PCI clock for PME# operation. When this bit is a “0”, it
indicates that no PCI clock is required for the function to generate
PME#.
The value of this bit is loaded from the PME_CK bit in the EEPROM
0x6 word.
2 - 0
0
RO
Power Management PCI Version
The value of this bit is loaded from the PME_VER[2:0] bits in the
EEPROM 0x6 word.
Wakeup Frame Control Register (Offset 0x021A): WFCR
This register holds control information programmed by the CPU to control the transmit module function.
Bit
Default
R/W
Description
15 - 8
0x00
RO
Reserved
7
0
RW
MPRXE
Magic Packet RX Enable
When set, it enables the magic packet pattern detection.
When reset, the magic packet pattern detection is disabled.
6 - 4
0x0
RO
Reserved
3
0
RW
WF3E
Wake up Frame 3 Enable
When set, it enables the wake up frame 3 pattern detection.
When reset, the wake up frame pattern detection is disabled.
2
0
RW
WF2E
Wake up Frame 2 Enable
When set, it enables the wake up frame 2 pattern detection.
When reset, the wake up frame pattern detection is disabled.
1
0
RW
WF1E
Wake up Frame 1 Enable
When set, it enables the wake up frame 1 pattern detection.
When reset, the wake up frame pattern detection is disabled.
0
RW
WF0E
Wake up Frame 0 Enable
When set, it enables the wake up frame 0 pattern detection.
When reset, the wake up frame pattern detection is disabled.
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