參數(shù)資料
型號(hào)： PIC12F635T-I/SN
廠(chǎng)商： Microchip Technology
文件頁(yè)數(shù)： 47/74頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH 1KX14 8SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 3,300
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 帶卷 (TR)
配用： AC162057-ND - MPLAB ICD 2 HEADER 14DIP
Micrel, Inc.
KSZ8841-PMQL
October 2007
51
M9999-100407-1.5
Wakeup Frame 2 Byte Mask 1 Register (Offset 0x0246): WF2BM1
This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 2; setting bit 15 selects the 32nd byte of the Wake up frame 2.
Bit
Default
R/W
Description
15 - 0
--
RW
WF2BM1
Wake up Frame 2 Byte Mask 1
The next 16 bytes mask covering bytes 17 to 32 of a wake up frame 2
pattern.
Wakeup Frame 2 Byte Mask 2 Register (Offset 0x0248): WF2BM2
This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 2; setting bit 15 selects the 48th byte of the Wake up frame 2.
Bit
Default
R/W
Description
15 - 0
--
RW
WF2BM2
Wake up Frame 2 Byte Mask 2
The next 16 bytes mask covering bytes 33 to 48 of a wake up frame 2
pattern.
Wakeup Frame 2 Byte Mask 3 Register (Offset 0x024A): WF2BM3
This register contains the last 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 2; setting bit 15 selects the 64th byte of the Wake up frame 2.
Bit
Default
R/W
Description
15 - 0
--
RW
WF2BM2
Wake up Frame 2 Byte Mask 3
The last 16 bytes mask covering bytes 49 to 64 of a wake up frame 2
pattern.
Wakeup Frame 3 CRC0 Register (Offset 0x0250): WF3CRC0
This register contains the expected CRC values of the Wake up frame 3 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default
R/W
Description
15 - 0
--
RW
WF3CRC0
Wake up Frame 3 CRC (lower 16 bits)
The expected CRC value of a wake up frame 3 pattern.
Wakeup Frame 3 CRC1 Register (Offset 0x0252): WF3CRC1
This register contains the expected CRC values of the Wake up frame 3 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default
R/W
Description
15 - 0
--
RW
WF3CRC1
Wake up Frame 3 CRC (upper 16 bits)
The expected CRC value of a wake up frame 3 pattern.
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