參數(shù)資料
型號: PIC14000-04I/SP
廠商: Microchip Technology
文件頁數(shù): 131/153頁
文件大小: 0K
描述: IC MCU OTP 4KX14 A/D 28DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 15
系列: PIC® 14
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: 斜率 A/D
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
配用: ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 79
PIC14000
10.4
Low-Voltage Detector
The PIC14000 contains an integrated low-voltage
detector. The supply voltage is divided and compared
to the bandgap reference output. If the supply voltage
(VDD) falls below VTRIP-, then the low-voltage detector
will cause LVD (PCON<0>) to be reset. This bit can be
read by software to determine if a low voltage condition
occurred. This bit must be set by software.
The nominal values of the low-voltage detector trip
points are as follows:
VTRIP- = 2.55V
VTRIP+ = 2.60V
Hysteresis (VTRIP+ – VTRIP-) = 55 mV
10.5
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
10.5.1
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specied. See Electrical Specications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, “
Power-up Trouble Shooting.”
10.5.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a xed 72 ms (nominal)
time-out on power-up only, from POR. The power-up
timer operates from a local internal oscillator. The chip
is kept in reset as long as PWRT is active. The PWRT
delay allows the VDD to rise to an acceptable level. A
conguration bit, PWRTE, can disable (if set, or unpro-
grammed) or enable (if cleared, or programmed) the
power-up timer.
The power-up timer delay will vary from chip to chip
and due to VDD and temperature.
10.5.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over. This guarantees that the crystal
oscillator or resonator has started and stabilized.
10.5.4
IN OSCILLATOR START-UP
There is an 8-cycle delay in IN mode to ensure stability
only after a Power-on Reset (POR) or wake-up from
SLEEP.
TABLE 10-3:
STATUS BITS AND THEIR SIGNIFICANCE
POR
TO
PD
Meaning
01
1
Power-On Reset
00
X
Illegal, TO is set on POR
0X
0
Illegal, PD is set on POR
10
1
WDT reset during normal operation
10
0
WDT time-out wakeup from sleep
11
1
MCLR reset during normal operation
11
0
MCLR reset during SLEEP or HIBERNATE, or interrupt wake-up from
SLEEP or HIBERNATE.
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