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參數(shù)資料
型號： PIC14000-04I/SP
廠商： Microchip Technology
文件頁數(shù)： 96/153頁
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D 28DIP
產(chǎn)品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 15
系列： PIC® 14
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
連通性： I²C
外圍設備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： 斜率 A/D
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
配用： ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 47
PIC14000
7.4
Multi-Master Operation
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time,
arbitration and synchronization occur.
7.4.1
ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 7-11) and turns off its data output stage. A
master which lost arbitrating can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning
master-transmitter may be addressing it.
Arbitration is not allowed between:
A repeated START
A STOP and a data bit
A repeated START and a STOP
Care needs to be taken to ensure that these conditions
do not occur.
7.4.2
CLOCK SYNCHRONIZATION
Clock synchronization occurs after the devices have
started
arbitration.
This
is
performed
using
a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high
transition of this clock may not change the state of the
SCL line, if another device clock is still within its low
period. The SCL line is held low by the device with the
longest low period. Devices with shorter low periods
enter a high wait-state, until the SCL line comes high.
When the SCL line comes high, all devices start
counting off their high periods. The rst device to
complete its high period will pull the SCL line low. The
SCA line high time is determined by the device with the
shortest high period. This is shown in the Figure 7-12.
FIGURE 7-11: MULTI-MASTER
ARBITRATION (2 MASTERS)
FIGURE 7-12: I2C CLOCK
SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1≠ SDA
DATA 1
DATA 2
SDA
SCL
wait
state
start counting
HIGH period
CLK
1
CLK
2
SCL
counter
reset
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PIC14000-20/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC14000-20/SP 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC14000-20/SS 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC14000-20I/P 制造商:Microchip Technology Inc 功能描述:MCU 8BIT PIC14 RISC 7KB EPROM 5V - Bulk
PIC14000-20I/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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