參數(shù)資料
型號(hào): PIC16C432-E/P
廠(chǎng)商: Microchip Technology
文件頁(yè)數(shù): 36/70頁(yè)
文件大?。?/td> 0K
描述: IC MCU CMOS 8-BIT 20MHZ 2K 20DIP
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: LIN(本地互連網(wǎng)絡(luò))
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 12
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類(lèi)型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
配用: AC164029-ND - MODULE SKT PROMATEII 20DIP/SSOP
DVA16XP201-ND - ADAPTER DEVICE FOR MPLAB-ICE
2002 Microchip Technology Inc.
Preliminary
DS41140B-page 39
PIC16C432
7.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
The
CMIE
bit
(PIE1<6>)
and
the
PEIE
bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
Any read or write of CMCON. This will end the
mismatch condition.
b)
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
7.7
Comparator Operation During
SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake-up the device from SLEEP mode when enabled.
While the comparator is powered up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = 111, before entering SLEEP.
If the device wakes up from SLEEP, the contents of the
CMCON register are not affected.
7.8
Effects of a RESET
A device RESET forces the CMCON register to its
RESET state. This forces the comparator module to be
in the Comparator RESET mode, CM<2:0> = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered down during the RESET interval.
7.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup may occur. A
maximum
source
impedance
of
10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
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