參數(shù)資料
型號: PIC16C432-E/P
廠商: Microchip Technology
文件頁數(shù): 51/70頁
文件大小: 0K
描述: IC MCU CMOS 8-BIT 20MHZ 2K 20DIP
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: LIN(本地互連網(wǎng)絡(luò))
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
配用: AC164029-ND - MODULE SKT PROMATEII 20DIP/SSOP
DVA16XP201-ND - ADAPTER DEVICE FOR MPLAB-ICE
2002 Microchip Technology Inc.
Preliminary
DS41140B-page 53
PIC16C432
9.5
Interrupts
The PIC16C432 has 4 sources of interrupt:
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts (pins RB<7:4>)
Comparator interrupt
LIN Bus wake-up can be wired to RB0, or compar-
ator
The interrupt control register (INTCON) and the Periph-
eral Interrupt Register (PIR1) record individual interrupt
requests in flag bits. INTCON and PIR1 have individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which re-
enables all unmasked interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs (Figure 9-
16). The latency is the same for one or two cycle
instructions. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests.
FIGURE 9-15:
INTERRUPT LOGIC
Note 1: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
2: When an instruction that clears the GIE bit
is executed, any interrupts that were
pending for execution in the next cycle are
ignored. The CPU will execute a NOP in the
cycle immediately following the instruction
which clears the GIE bit. The interrupts
which were ignored are still pending to be
serviced when the GIE bit is set again.
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
PEIE
Wake-up
(If in SLEEP mode)
Interrupt
to CPU
CMIE
CMIF
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